公开(公告)号：US20180203672A1

公开(公告)日：2018-07-19

申请号：US15409778

申请日：2017-01-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Steven R. Carlough ,  Klaus M. Kroener ,  Silvia Melitta Mueller ,  Andreas Wagner

IPC分类号： G06F7/72 ,  G06F7/48

CPC分类号： G06F7/729 ,  G06F7/48

摘要： A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.

公开(公告)号：US20180113678A1

公开(公告)日：2018-04-26

申请号：US15298938

申请日：2016-10-20

申请人： Advanced Micro Devices, Inc.

发明人： Greg Sadowski ,  Wayne Burleson

IPC分类号： G06F7/48

CPC分类号： G06F7/4824 ,  G06F7/729

摘要： A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

公开(公告)号：US20140129601A1

公开(公告)日：2014-05-08

申请号：US14151751

申请日：2014-01-09

申请人： Eric B. Olsen

发明人： Eric B. Olsen

IPC分类号： G06F7/483

CPC分类号： G06F7/483 ,  G06F7/729 ,  G06F9/30025

摘要： Methods and systems for conversion of binary data to residue data, and for conversion of residue data to binary data, allow fully extensible operation with related methods and systems for residue number based ALUs, processors and other hardware. In one or more embodiments, a residue to binary data converter apparatus comprises a mixed radix to fixed radix conversion apparatus. In one or more embodiments, a mixed radix converter apparatus assists internal processing of a related residue number based ALU, processor or other hardware.

摘要翻译： 将二进制数据转换为残差数据以及将残差数据转换为二进制数据的方法和系统允许使用相关方法和系统进行完全可扩展的操作，用于基于残差数量的ALU，处理器和其他硬件。 在一个或多个实施例中，二进制数据转换器装置的残差包括到固定基数转换装置的混合基数。 在一个或多个实施例中，混合基座转换器装置协助对基于ALU，处理器或其他硬件的相关残留号码的内部处理。

公开(公告)号：US07165085B2

公开(公告)日：2007-01-16

申请号：US11106109

申请日：2005-04-14

申请人： Steven R. Robinson ,  William A. Chren, Jr.

发明人： Steven R. Robinson ,  William A. Chren, Jr.

IPC分类号： G06F7/38

CPC分类号： G06F7/729 ,  G06F5/01

摘要： A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi–mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj. Another modulo mi,j scaling unit includes a barrel shifter-based arithmetic circuit, and a dynamic storage unit coupled to the arithmetic circuit to store the output of the arithmetic circuit.

摘要翻译： 模R加法器和用于RNS的模m，i，j比例缩放单元。 该加法器包括一个模数转换器，以及耦合到桶形移位器以存储桶形移位器的输出的动态存储单元。 在优选实施例中，动态存储单元包括用于桶形移位器的每个输出线的一个动态锁存器，每个动态锁存器包括与逆变器级联的时钟反相器。 一个模数m i，j个缩放单元包括执行残差转换和算术运算两者的修改后的模数移位器。 在不使用组合逻辑的情况下执行残余转换。 在一个优选实施例中，经修改的桶形移位器通过复制正常列的所有模m i / / SUB来执行残余转换 >输入线，它们是等同的模m m。 另一个模数转换单元包括基于桶形移位器的运算电路，以及耦合到运算电路以存储运算电路的输出的动态存储单元。

公开(公告)号：US07010560B2

公开(公告)日：2006-03-07

申请号：US10051280

申请日：2002-01-22

申请人： Atsushi Shimbo

发明人： Atsushi Shimbo

IPC分类号： G06F7/38

CPC分类号： G06F7/729

摘要： A modular arithmetic apparatus has a plurality of base parameter sets in read only memories. A base selection unit in the modular arithmetic apparatus selects one of the base parameters sets according to an input modulus p. A plurality of operation units 30, in the modular arithmetic apparatus, perform an arithmetic operation according to the selected base parameter set in parallel and obtain an arithmetic result.

摘要翻译： 模数运算装置在只读存储器中具有多个基本参数集。 模块运算装置中的基本选择单元根据输入模数p选择一个基本参数集。 在该运算装置中，多个运算单元30根据并列设定的基准参数进行算术运算，得到运算结果。

公开(公告)号：US06697831B2

公开(公告)日：2004-02-24

申请号：US10085760

申请日：2002-02-28

申请人： Jordan C. Cookman ,  Ping Dong

发明人： Jordan C. Cookman ,  Ping Dong

IPC分类号： G06F738

CPC分类号： G06F7/72 ,  G06F7/729 ,  H04L27/00

摘要： A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

摘要翻译： 提供了一种允许使用很少或没有分割操作来计算多模转换（MMC）输出的方法和装置。 代替分割运算，乘法和逻辑移位运算用于产生伪商和伪余数，这可以在最终步骤中进行校正，以产生正确的MMC输出。 这允许更有效的实现，因为除法通常比乘法和逻辑移位效率低。 该方法和装置在可以划分成任何编号系统中具有不同数字位数的子商品的MMC输入上操作。 根据从长分割技术导出的过程，对每个子商进行乘法和逻辑移位操作。

公开(公告)号：US20020099749A1

公开(公告)日：2002-07-25

申请号：US10051280

申请日：2002-01-22

发明人： Atsushi Shimbo

IPC分类号： G06F007/38

CPC分类号： G06F7/729

摘要： A modular arithmetic apparatus has a plurality of base parameter sets in read only memories. A base selection unit in the modular arithmetic apparatus selects one of the base parameters sets according to an input modulus p. A plurality of operation units 30, in the modular arithmetic apparatus, perform an arithmetic operation according to the selected base parameter set in parallel and obtain an arithmetic result.

摘要翻译： 模数运算装置在只读存储器中具有多个基本参数集。 模块运算装置中的基本选择单元根据输入模数p选择一个基本参数集。 在该运算装置中，多个运算单元30根据并列设定的基准参数进行算术运算，得到运算结果。

公开(公告)号：US06256656B1

公开(公告)日：2001-07-03

申请号：US09221911

申请日：1998-12-28

申请人： Carroll Philip Gossett ,  Nancy Cam Winget

发明人： Carroll Philip Gossett ,  Nancy Cam Winget

IPC分类号： G06F700

CPC分类号： G06F7/729 ,  G06F7/721

摘要： The integers involved in the computation are embedded into a modular system whose index (i.e., its modulus) is an integer M that is bigger than all of these integers involved. In other words, these integers are treated not as belonging to ordinary integers anymore, but as “modular integers” belonging to the modular system indexed by M. Having completed the embedding, CRT provides the bridge which connects the single modular system indexed by M (ZM) with a collection of k modular systems indexed by m1,m2, . . . , mk respectively (Zm1, Zm2, . . . , Zmk), where M factorizes as m1*m2*m3* . . . *mk, and where each mi is slightly smaller than single precision. Then, after numbers are manipulated within modular arithmetic, the answer is reconstructed via the algorithm of CRT, also known as CRA. Finally, the present invention introduces the process of dinking that overcomes the major weakness of implementing division with modular arithmetic. Particularly, within a composite modular arithmetic system, any theoretically impossible modular division is altered slightly [dinked] to a theoretical possible modular division whose quotient is closed enough to the true quotient sought, thus allowing all four arithmetic operations of modular arithmetic in high precision computation.

摘要翻译： 涉及计算的整数嵌入到一个模块化系统中，它的索引（即它的模数）是一个大于所有这些整数的整数M。 换句话说，这些整数被视为不属于普通的整数，而是属于由M索引的模块化系统的“模块化整数”。完成了嵌入后，CRT提供了连接由M（ ZM），其中包含由m1，m2指定的k个模块化系统的集合。 。 。 ，mk（Zm1，Zm2，...，Zmk），其中M因子分解为m1 * m2 * m3 *。 。 。 * mk，其中每个mi略小于单精度。 然后，在模数运算中操作数字之后，通过CRT的算法（也称为CRA）重构答案。 最后，本发明介绍了采用模块化算法实现划分的主要缺陷的烙印过程。 特别地，在复合模数运算系统中，任何理论上不可能的模块划分被稍微改变为理论上可能的模分割，其商商被关闭到满足所寻求的真商，从而允许在高精度计算中的所有四个算术运算 。

公开(公告)号：US5107451A

公开(公告)日：1992-04-21

申请号：US472237

申请日：1990-01-30

申请人： Theodore L. Houk

发明人： Theodore L. Houk

IPC分类号： G06E1/06 ,  G06F7/72

CPC分类号： G06E1/065 ,  G06F7/729

摘要： A residue number system multiplication overflow detection processor generates either a VALID signal or an INVALID signal indicating whether multiplication overflow has occurred. Operands X and Y are received in residue representation and are multiplied in a multiplier. The X and Y operands are also converted to mixed base representation. The mixed base representations of the operands are compared in order to generate magnitude measures indicative of the magnitude of each of the operands. These magnitude measures and a mixed base representation of the product are used to generate the VALID and INVALID signals. The invention is particularly well-suited to be implemented using optical technologies.

摘要翻译： 残差号系统乘法溢出检测处理器生成表示是否发生乘法溢出的VALID信号或INVALID信号。 以残差表示方式接收操作数X和Y，并将其乘以乘数。 X和Y操作数也被转换为混合的基数表示。 比较操作数的混合基本表示，以便产生指示每个操作数的大小的幅度测量。 这些幅度测量和产品的混合基本表示用于生成VALID和INVALID信号。 本发明特别适合于使用光学技术实现。

公开(公告)号：US4107783A

公开(公告)日：1978-08-15

申请号：US764994

申请日：1977-02-02

申请人： Alan Huang

发明人： Alan Huang

IPC分类号： G06F7/72 ,  G06F7/38

CPC分类号： G06F7/729

摘要： A system for processing arithmetic information wherein the residue number system is used to partition a calculation into several simpler calculations each of which can be processed in parallel with complete independence. These segments are computationally simple such that all the arithmetic interactions can be ennumerated as mathematical "mappings". By routing signals through various "mappings" a number is encoded into residue form, processed in various ways, and eventually decoded back to a normal number system. The signals are routed in a manner to reflect calculations involving a plurality of operands and operations. By routing several signals in close sequence, calculations are pipelined. By routing different types of signals independently several calculations are carried out substantially simultaneously with each other. Detection of abnormalities in the signal from a given segment is used to exclude the segment from the decoding process thus preserving the correctness of the overall calculations notwithstanding an error in part of the computation.

摘要翻译： 一种用于处理算术信息的系统，其中残差编号系统用于将计算分割成几个更简单的计算，每个计算可以完全独立地并行处理。 这些段在计算上是简单的，使得所有算术交互可以被枚举为数学“映射”。 通过通过各种“映射”路由信号，数字被编码成残差形式，以各种方式处理，并最终被解码回正常数字系统。 这些信号以一种方式被路由以反映涉及多个操作数和操作的计算。 通过几个信号的顺序排列，流水线计算。 通过独立地路由不同类型的信号，几个计算基本上彼此同时进行。 使用来自给定段的信号中的异常的检测用于从解码过程中排除该段，从而保持整个计算的正确性，尽管部分计算中存在错误。