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公开(公告)号：US20240044042A1
公开(公告)日：2024-02-08
申请号：US18380897
申请日：2023-10-17
Inventor： Tadaaki Kaneko , Yasunori Kutsuma , Koji Ashida , Ryo Hashimoto
CPC classification number: C30B23/063 , C30B29/36 , C30B23/025 , H01L21/02378 , H01L21/02389 , H01L21/02433 , H01L21/02529 , H01L21/02631
Abstract: Disclosed is a method for using a SiC container (3) in which Si vapor and C vapor are generated in the internal space during the heat treatment. The SiC container may be heated in Si atmosphere to grow an epitaxial layer of single crystalline SiC on the underlying substrate housed in the internal space. The SiC container may be heated in a TaC container of a material including TaC supplemented with a source of Si to grow an epitaxial layer of single crystalline SiC on the underlying substrate housed in the internal space.
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公开(公告)号：US20240020814A1
公开(公告)日：2024-01-18
申请号：US18250710
申请日：2021-10-27
Inventor： Tadaaki KANEKO , Daichi DOJIMA
CPC classification number: G06T7/0004 , H01L21/02378 , H01L21/02433 , H01L21/0475 , G06T2207/30148
Abstract: An object of the present invention is to provide a novel technique for evaluating a heat treatment environment. The present invention is a method for evaluating a heat treatment environment, the method comprising an image acquisition step of acquiring an image by making an electron beam incident at an incident angle inclined with respect to a normal line of a {0001} plane of a heat-treated silicon carbide substrate and an environment evaluation step of evaluating a heat treatment environment of the silicon carbide substrate on a basis of on contrast information of the image.
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公开(公告)号：US20230352551A1
公开(公告)日：2023-11-02
申请号：US18220397
申请日：2023-07-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tung Ying Lee , Kai-Tai Chang , Meng-Hsuan Hsiao
IPC: H01L29/423 , H01L21/8234 , H01L29/66 , H01L21/02 , H01L21/8238
CPC classification number: H01L29/42392 , H01L21/823431 , H01L29/66287 , H01L21/02433 , H01L29/66553 , H01L21/823864
Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
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公开(公告)号：US20230352301A1
公开(公告)日：2023-11-02
申请号：US18304125
申请日：2023-04-20
Applicant: ASM IP Holding, B.V.
Inventor： Rami Khazaka
IPC: H01L21/02 , C30B25/18 , C30B29/52 , C30B33/08 , C30B31/06 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/786 , H01L21/3065
CPC classification number: H01L21/02532 , C30B25/18 , C30B29/52 , C30B33/08 , C30B31/06 , H01L29/42392 , H01L29/0669 , H01L29/66439 , H01L29/0847 , H01L29/78681 , H01L21/02433 , H01L21/02592 , H01L21/0262 , H01L21/3065
Abstract: Methods and systems for selectively forming crystalline boron-doped silicon germanium on a surface of a substrate. The methods can be used to selectively form the boron-doped silicon germanium within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.
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15.发明授权
公开(公告)号：US11804519B2
公开(公告)日：2023-10-31
申请号：US17239931
申请日：2021-04-26
Applicant: FLOSFIA INC. , National Institute for Material Science
Inventor： Yuichi Oshima , Katsuaki Kawara
CPC classification number: H01L29/045 , H01L21/0242 , H01L21/02433 , H01L21/02565 , H01L21/02595 , H01L21/02609 , H01L29/247
Abstract: A crystalline multilayer structure having a high-quality crystalline layer and a semiconductor device employing such a crystalline multilayer structure are provided. A crystalline multilayer structure, including a first crystalline layer having a first crystal, and a second crystalline layer stacked on the first crystalline layer and having a second crystal, wherein the first crystal includes polycrystalline κ-Ga2O3 and the second crystal is a single crystal of a crystalline oxide.
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公开(公告)号：US20230343589A1
公开(公告)日：2023-10-26
申请号：US17779474
申请日：2021-04-15
Applicant: ENKRIS SEMICONDUCTOR, INC.
Inventor： Kai Cheng , Liyang Zhang
IPC: H01L21/02 , H01L21/768 , H01L21/308 , H01L23/48
CPC classification number: H01L21/0254 , H01L21/76898 , H01L21/02381 , H01L21/02433 , H01L21/02164 , H01L21/0217 , H01L21/3081 , H01L21/3086 , H01L23/481
Abstract: The disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first group III nitride epitaxial layer disposed on a support substrate, a silicon substrate, a bonding layer and a second group III nitride epitaxial layer; wherein the first group III nitride epitaxial layer is bonded to the silicon substrate by the bonding layer; through-silicon-vias are formed in the silicon substrate, and first through-holes are formed in the bonding layer, wherein the through-silicon-vias communicate with the first through-holes; and the second group III nitride epitaxial layer is disposed within the first through-holes and the through-silicon-vias and on the silicon substrate, wherein the second group III nitride epitaxial layer is coupled to the first group III nitride epitaxial layer. Since the depth to width ratio of the through-silicon-via(s) is great, the dislocation extension within the second group III nitride epitaxial layer is limited, and the probability of dislocation annihilation in the sidewalls of the through-silicon-via(s) is increased, such that the second III nitride epitaxial layer with low dislocation density can be formed, and the quality of the epitaxial layer is improved.
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公开(公告)号：US11773507B2
公开(公告)日：2023-10-03
申请号：US16905337
申请日：2020-06-18
Applicant: SHOWA DENKO K.K.
Inventor： Tomohiro Shonai , Masakazu Kobayashi , Masanori Yamada
IPC: C30B29/36 , C30B23/02 , C01B32/956 , H01L29/16 , H01L21/02
CPC classification number: C30B29/36 , C01B32/956 , C30B23/02 , C30B23/025 , H01L29/1608 , C01P2002/78 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02609 , H01L21/02631
Abstract: A SiC single crystal, including: a seed crystal; a first growth portion formed in a direction that is substantially orthogonal to a direction; a second growth portion formed in a direction that is substantially orthogonal to the direction and substantially orthogonal to the direction in which the first growth portion is formed; a third growth portion that is formed on a surface of the seed crystal opposite the first growth portion; and a fourth growth portion that is formed on a surface of the seed crystal opposite the second growth portion.
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公开(公告)号：US11742405B2
公开(公告)日：2023-08-29
申请号：US17346378
申请日：2021-06-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tung Ying Lee , Kai-Tai Chang , Meng-Hsuan Hsiao
IPC: H01L29/423 , H01L21/8234 , H01L29/66 , H01L21/02 , H01L21/8238
CPC classification number: H01L29/42392 , H01L21/02433 , H01L21/823431 , H01L21/823864 , H01L29/66287 , H01L29/66553
Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
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19.发明授权
公开(公告)号：US11715635B2
公开(公告)日：2023-08-01
申请号：US17525516
申请日：2021-11-12
Applicant: UNM RAINFOREST INNOVATIONS
Inventor： Morteza Monavarian , Daniel Feezell , Andrew Aragon , Saadat Mishkat-Ul-Masabih , Andrew Allerman , Andrew Armstrong , Mary Crawford
IPC: H01L21/3065 , H01L21/306 , H01L21/02
CPC classification number: H01L21/02057 , H01L21/0254 , H01L21/02389 , H01L21/02433 , H01L21/3065 , H01L21/30612
Abstract: A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.
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公开(公告)号：US20230166967A1
公开(公告)日：2023-06-01
申请号：US17992905
申请日：2022-11-22
Applicant: ROHM CO., LTD.
Inventor： Daisuke KAMINISHI , Martin Wilfried HELLER , Toma FUJITA
CPC classification number: B81C1/00238 , H01L21/02636 , H01L21/02433 , B81B2201/0235
Abstract: A MEMS sensor includes: a first substrate having a cavity partially exposed on the surface of the first substrate; an electrode of a sensor element provided on the first substrate and arranged in the cavity; a support portion provided on the first substrate and configured to support the electrode; an element isolation portion formed on the first substrate so as to cover the support portion and configured to electrically isolate the electrode and the support portion from each other; an epitaxial growth layer formed on the electrode and the element isolation portion of the first substrate; and a second substrate bonded to the first substrate and configured to cover the sensor element, wherein the epitaxial growth layer has a monocrystalline portion arranged on the electrode and a polycrystalline portion arranged on the element isolation portion.
