公开(公告)号：US20030053553A1

公开(公告)日：2003-03-20

申请号：US10223750

申请日：2002-08-20

申请人： InterDigital Technology Corporation

发明人： David Norton Critchlow ,  Moshe Yehushua ,  Graham Martin Avis ,  Wade Lyle Heimbigner ,  Karle Joseph Johnson ,  George Alan Wiley

IPC分类号： H04L027/04

CPC分类号： H04L25/03343 ,  H03B28/00 ,  H03C3/00 ,  H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H04L2025/03375 ,  H04L2025/03477

摘要： A subscriber unit has a processor. The processor provides an output phase signal corresponding to a selected output digital frequency. A tuning register buffers the phase signal. A lookup table has two sets of predefined stored values pertaining to the amplitude of a signal for a single quadrant. The predefined stored values comprise coarse angle approximations and fine angle approximations. A sine and cosine generator receives the phase signal and generates sine and cosine waveforms utilizing amplitude values obtained from the lookup table. The phase signal includes phase data and specifies the quadrant and the algebraic sign of the phase data. The sine and cosine generator accessing the lookup table differently depending upon the quadrant and sine of the phase data, such that the lookup table provides an amplitude value from the sets of predefined stored values based on the phase data. A modulator combines the sine and cosine waveforms to produce the selected output digital frequency and modulates digital frequency.

摘要翻译： 用户单元具有处理器。 处理器提供对应于所选输出数字频率的输出相位信号。 调谐寄存器缓冲相位信号。 查找表具有两组与单个象限的信号幅度有关的预定义存储值。 预定义的存储值包括粗略角近似和细角近似。 正弦和余弦发生器接收相位信号，并使用从查找表获得的振幅值产生正弦和余弦波形。 相位信号包括相位数据，并指定相位数据的象限和代数符号。 正弦和余弦发生器根据相位数据的象限和正弦来不同地访问查找表，使得查找表基于相位数据从预定义的存储值集合提供振幅值。 调制器组合正弦和余弦波形以产生选定的输出数字频率并调制数字频率。

公开(公告)号：US6097259A

公开(公告)日：2000-08-01

申请号：US147053

申请日：1998-09-28

申请人： Yoshiko Saito ,  Mitsuru Uesugi

发明人： Yoshiko Saito ,  Mitsuru Uesugi

IPC分类号： H03M7/32 ,  H04L27/20 ,  H04L27/36

CPC分类号： H04L27/2092

摘要： A modulator and modulation method for orthogonally modulating digital baseband signals include interpolation filters that frequency convert the frequencies of an in-phase component and a quadrature phase component of a digital baseband signal to four times the frequency of an intermediate frequency. .DELTA..SIGMA. modulation circuits are provided and .DELTA..SIGMA. modulate the frequency converted signals. A low pass filter is provided to remove unnecessary components from the .DELTA..SIGMA. modulated signals. A switching circuit selects a signal that has passed through the low pass filter according to an order of an in-phase component, a code inverted component of a quadrature phase component, a code inverted component of the in-phase component and the quadrature phase component, and outputs these signals as a digital orthogonal signal. An N bit D/A converter converts the digital orthogonal signals into analog orthogonal signals.

摘要翻译： PCT No.PCT / JP98 / 00657 Sec。 371日期：1998年9月28日 102（e）日期1998年9月28日PCT提交1998年2月17日PCT公布。 第WO98 / 38775号公报 日期1998年9月3日用于对数字基带信号进行正交调制的调制器和调制方法包括将数字基带信号的同相分量和正交相位分量的频率频率转换成中频频率的四倍的内插滤波器。 提供DELTA SIGMA调制电路，DELTA SIGMA调制变频信号。 提供低通滤波器以从DELTA SIGMA调制信号中去除不必要的分量。 开关电路根据同相分量的顺序，正交相位分量的代码反相分量，同相分量的码反相分量和正交相位分量来选择已经通过低通滤波器的信号 并输出这些信号作为数字正交信号。 N位D / A转换器将数字正交信号转换为模拟正交信号。

公开(公告)号：US5990755A

公开(公告)日：1999-11-23

申请号：US68118

申请日：1998-06-02

申请人： Yashiro Takaaki

发明人： Yashiro Takaaki

IPC分类号： H04L27/20 ,  H03C3/00

CPC分类号： H04L27/2092 ,  H04L27/2032 ,  H04L27/2067

摘要： Ramp period detecting circuit 101 outputs signal Tc that indicates the start and end of the ramp period. Two-dimensional quadrature coordinates (I.alpha.,Q.alpha.) and (I.beta.,Q.beta.) are output alternately. Coordinate accumulator 106 accumulates I.alpha. which is +1 or -1 corresponding to each odd piece of two-bit data; coordinate accumulator 107 accumulates Q.alpha. which is 0 corresponding to each even piece of two-bit data. Response waveforms from a digital lowpass filter (or rise/fall ramp waveforms) corresponding to signal Tc and outputs from coordinate accumulators 106 and 107, namely accumulated values of I.alpha. and Q.alpha., are alternately read from storage unit 112.

摘要翻译： PCT No.PCT / JP96 / 03482 Sec。 371日期1998年6月2日 102（e）1998年6月2日PCT 1996年11月27日PCT PCT。 公开号WO97 / 20416 PCT 日期1997年6月6日，电压周期检测电路101输出指示斜坡期间的开始和结束的信号Tc。 交替输出二维正交坐标（I alpha，Q alpha）和（I beta，Q beta）。 坐标累加器106累积对应于每个奇数二位数据的+1或-1的I alpha; 坐标累加器107累积对应于每个偶数位的两位数据为0的Qα。 从存储单元112交替地读取来自对应于信号Tc的数字低通滤波器（或上升/下降斜坡波形）和来自坐标累加器106和107的输出的响应波形，即I alpha和Q alpha的累积值。

公开(公告)号：US5864492A

公开(公告)日：1999-01-26

申请号：US774300

申请日：1996-12-24

申请人： Philippe Roger Sadot

发明人： Philippe Roger Sadot

IPC分类号： G06F1/03 ,  H04L27/20 ,  H04L27/36 ,  G06F1/02

CPC分类号： H04L27/365 ,  G06F1/0328 ,  H04L27/2092 ,  G06F2211/902

摘要： A digital synthesizer for producing a digital frequency signal includes a phase accumulator for repeatedly accumulating a phase value to generate samples of a digital sawtooth signal and a look-up table of digital samples for converting the digital sawtooth signal to a digital waveshape signal. In order to reduce the effect of the quantization of the digital samples, the synthesizer also includes a randomizer for applying a randomizing factor to output digital samples for forming the digital frequency signal. The randomizer includes a randomizing factor generator connected to receive P bits of each digital sample for generating at least one randomizing bit and an summer for summing the remaining N bits of the digital sample and the at least one randomizing bit to generate a digital waveshape sample of the digital frequency signal.

摘要翻译： 用于产生数字频率信号的数字合成器包括相位累加器，用于重复累加相位值以产生数字锯齿波信号的样本和用于将数字锯齿波信号转换为数字波形信号的数字采样的查找表。 为了减少数字样本量化的效果，合成器还包括随机化器，用于将随机化因子应用于输出用于形成数字频率信号的数字样本。 随机化器包括随机化因子发生器，其被连接以接收每个数字样本的P位以产生至少一个随机化位和用于对数字样本的剩余N位和至少一个随机化位进行求和的加法器，以产生数字波形样本 数字频率信号。

公开(公告)号：US5705945A

公开(公告)日：1998-01-06

申请号：US684807

申请日：1996-07-22

申请人： Reginald Siang-Tze Wee

发明人： Reginald Siang-Tze Wee

IPC分类号： H04L27/12 ,  H04L27/20

CPC分类号： H04L27/122 ,  H04L27/2092

摘要： An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

摘要翻译： 描述了用于实现全数字频率合成系统的架构和系统。 频率合成系统具有计数序列保持表，该计数系列保持表包含由选择要连接到周期性输入参考频率计数器的整数的哪个系列的计数信号选择的一系列计数整数。 周期性输入参考频率计数器将对周期性输入参考频率的周期数进行计数，当计数器达到等于计数整数的计数数时，周期性输出频率将从逻辑电平切换到 另一个逻辑层面。 可以通过在计数保留表中选择一系列新的计数整数来选择新的周期性输出频率周期。 该架构的结构使其可以在自动逻辑设计系统中实现。

公开(公告)号：US5523726A

公开(公告)日：1996-06-04

申请号：US322833

申请日：1994-10-13

申请人： Brian W. Kroeger ,  Roy Stehlik

发明人： Brian W. Kroeger ,  Roy Stehlik

IPC分类号： H04L27/20 ,  H03C3/00 ,  H04L27/18

CPC分类号： H04L27/2092

摘要： A digital quadriphase-shift keying modulator is described which generates a modulated intermediate carrier frequency (IF) based on a desired number of samples for each input information bit. The design includes a ROM (or RAM) look-up table which stores digitized waveforms. The inphase and quadrature components of a complex baseband signal are translated to an IF at a multiple of the sampling rate simply by alternating the inphase and quadrature samples and alternating signs. The real IF output is produced by summing the inphase and quadrature signals.

摘要翻译： 描述了一种数字四相移键控调制器，其基于每个输入信息比特的期望数目的样本产生调制的中间载波频率（IF）。 该设计包括存储数字化波形的ROM（或RAM）查找表。 复杂基带信号的同相和正交分量简单地通过交替相位和正交样本和交替符号而以采样率的倍数转换为IF。 实际的IF输出是通过对同相和正交信号求和来产生的。

公开(公告)号：US5361047A

公开(公告)日：1994-11-01

申请号：US56899

申请日：1993-05-05

申请人： Yasuaki Takahara ,  Tomohiro Esaki ,  Shigeyuki Sudo ,  Teiji Okamoto

发明人： Yasuaki Takahara ,  Tomohiro Esaki ,  Shigeyuki Sudo ,  Teiji Okamoto

IPC分类号： H04L27/20

CPC分类号： H04L27/2092

摘要： A .pi./4 shift QPSK modulator for receiving digital signals and for outputting a modulated signal therefrom in accordance with each of the inputted digital signals. The .pi./4 QPSK modulator is utilized in a communication apparatus and includes a counter for counting the number of the inputted digital signals, a phase information arithmetic unit for receiving a value of an output from the counter and a value of each of the inputted digital signals for outputting phase information of the signal to be modulated, an arithmetic unit for performing an arithmetic operation on values representing an impulse response of the output phase information from the phase information arithmetic unit and outputting impulse response values in accordance therewith, and an accumulating unit for accumulating impulse response values outputted from the arithmetic unit and for performing an arithmetic operation for enabling generation of a .pi./4 shift QPSK modulated signal.

摘要翻译： 一种用于接收数字信号并根据每个输入的数字信号从其输出调制信号的π/ 4移位QPSK调制器。 pi / 4QPSK调制器用于通信设备中，并且包括用于对输入的数字信号的数量进行计数的计数器，用于接收来自计数器的输出值的相位信息运算单元和输入的数字信号的每一个的值 用于输出要调制的信号的相位信息的信号，用于对表示来自相位信息运算单元的输出相位信息的脉冲响应的值执行运算的运算单元，并输出与之相应的脉冲响应值;以及累积单元 用于累积从运算单元输出的脉冲响应值，并执行用于实现pi / 4移位QPSK调制信号的产生的算术运算。

公开(公告)号：US5325396A

公开(公告)日：1994-06-28

申请号：US940662

申请日：1992-09-04

申请人： David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson ,  George A. Wiley

发明人： David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson ,  George A. Wiley

IPC分类号： H04M1/00 ,  H03B28/00 ,  H03C3/00 ,  H03D3/00 ,  H04B1/40 ,  H04B3/00 ,  H04B7/00 ,  H04J3/02 ,  H04L25/03 ,  H04L27/00 ,  H04L27/18 ,  H04L27/20 ,  H04W84/16 ,  H03K3/80

CPC分类号： H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H03B28/00 ,  H03C3/00 ,  H04L2025/03375 ,  H04L2025/03477

摘要： A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

摘要翻译： 用于与无线用户通信系统中的基站进行无线通信的用户单元包括FIR芯片，DIF（数字中频）芯片，单个处理器芯片和无线电装置。 处理器芯片对数字语音输入信号进行转码以提供数字输入符号; 解调从基站接收的输出信号以提供数字输出符号; 并从数字输出符号合成数字语音输出信号。 FIR芯片FIR对数字输入符号进行滤波，并产生用于对处理器芯片中的代码转换和合成操作进行定时的定时信号。 DIF芯片通过直接数字合成（DDS）数字合成数字中频信号，并用滤波后的输入符号对数字中频信号进行调制，以提供调制中频输入​​信号。 无线电进一步处理调制的输入信号以传输到基站。

公开(公告)号：US5214396A

公开(公告)日：1993-05-25

申请号：US805647

申请日：1991-12-12

申请人： Byoung-Jin Cheon

发明人： Byoung-Jin Cheon

IPC分类号： H04L27/04 ,  H03K7/04 ,  H04L27/20

CPC分类号： H03K7/04 ,  H04L27/2092

摘要： A biphase shift keying modulation circuit includes: a clock pulse generator for generating system clock pulses; a random data generating unit for dividing the frequency of the system clock pulses to generate random digital data in synchronism with the divided clock pulses; a data conversion circuit for sequentially shifting the random digital data in synchronism with the system clock pulses and generating parallel shifted data which is multiplied by given resistive values and added to each other to provide an in-phase signal component, and for processing the shifted data and random digital data to provide a quadrature-phase signal component without a direct current component; a carrier wave oscillator for generating a carrier wave signal; and a modulating circuit for modulating the in-phase signal component and quadrature-phase signal component with the carrier wave signal and ninety degree phase-shifted carrier wave, respectively, in which the modulated signals are added to provide a phase modulated signal of flat envelope characteristics.

摘要翻译： 双相移键控调制电路包括：时钟脉冲发生器，用于产生系统时钟脉冲; 随机数据生成单元，用于分频系统时钟脉冲的频率，以产生与划分的时钟脉冲同步的随机数字数据; 数据转换电路，用于与系统时钟脉冲同步顺序地移位随机数字数据，并产生并行移位的数据，该并行移位数据与给定的电阻值相乘并相加，以提供同相信号分量，并用于处理移位的数据 和随机数字数据，以提供没有直流分量的正交相位信号分量; 用于产生载波信号的载波振荡器; 以及调制电路，用于分别与载波信号和九十度相移载波调制同相信号分量和正交相位信号分量，其中调制信号相加，以提供平面信号的相位调制信号 特点

公开(公告)号：US5146473A

公开(公告)日：1992-09-08

申请号：US658065

申请日：1991-02-20

申请人： David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson

发明人： David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson

IPC分类号： G06F1/035 ,  H03B28/00 ,  H03C3/00 ,  H03D3/00 ,  H04L23/00 ,  H04L25/03 ,  H04L27/00 ,  H04L27/04 ,  H04L27/06 ,  H04L27/12 ,  H04L27/20

CPC分类号： H04L25/03343 ,  H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H03B28/00 ,  H03C3/00 ,  H04L2025/03375 ,  H04L2025/03477

摘要： A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

摘要翻译： 用于与无线用户通信系统中的基站进行无线通信的用户单元包括FIR芯片，DIF（数字中频）芯片，单个处理器芯片和无线电装置。 处理器芯片对数字语音输入信号进行转码以提供数字输入符号; 解调从基站接收的输出信号以提供数字输出符号; 并从数字输出符号合成数字语音输出信号。 FIR芯片FIR对数字输入符号进行滤波，并产生用于对处理器芯片中的代码转换和合成操作进行定时的定时信号。 DIF芯片通过直接数字合成（DDS）数字合成数字中频信号，并用滤波后的输入符号对数字中频信号进行调制，以提供调制中频输入​​信号。 无线电进一步处理调制的输入信号以传输到基站。