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    Epitaxial growth process for iii-v mixed-compound semiconductor crystals
    12.
    发明授权
    Epitaxial growth process for iii-v mixed-compound semiconductor crystals 失效
    III-V混合化合物半导体晶体的外延生长工艺

    公开(公告)号：US3839082A

    公开(公告)日：1974-10-01

    申请号：US25817572

    申请日：1972-05-31

    申请人： HITACHI LTD

    发明人： KASANO H ,  KURATA K

    IPC分类号： B05D3/02 ,  C30B25/02 ,  C30B29/40 ,  B44D1/18 ,  H01L7/36

    CPC分类号： C30B25/02 ,  C30B29/40 ,  Y10S148/005 ,  Y10S148/007 ,  Y10S148/064 ,  Y10S148/065 ,  Y10S148/067 ,  Y10S148/072 ,  Y10S438/916 ,  Y10S438/933

    摘要： A process for epitaxially growing a III-V mixed-compound semiconductor crystal composed of three or more components on a semiconductor substrate made of a different material from the crystal utilizes a disproportionation reaction in a halogen vapor transport. The back and side faces of the substrate are covered with a material chemically stable against halogen or halides at the epitaxial temperature of the mixed crystal, and a compound, selected from among the crystal-composing compounds which has a relatively low epitaxial temperature, is epitaxially grown on the substrate maintained at said temperature. The temperature of the substrate is then increased to the epitaxial temperature of the crystal, and epitaxial growth of the crystal is carried out on the compound.

    摘要翻译： 在由与晶体不同的材料制成的半导体衬底上由三个或更多个组分组成的III-V混合化合物半导体晶体外延生长的方法利用卤素蒸气传输中的歧化反应。 衬底的背面和侧面在混合晶体的外延温度下用对卤素或卤化物化学稳定的材料覆盖，并且选自具有相对低的外延温度的晶体组成化合物中的化合物是外延的 在保持在所述温度下的基材上生长。 然后将衬底的温度增加到晶体的外延温度，并且对该化合物进行晶体的外延生长。

    Process for preparing high sensitivity semiconductive magnetoresistance element
    15.
    发明授权
    Process for preparing high sensitivity semiconductive magnetoresistance element 失效
    制备高灵敏度半导体磁阻元件的方法

    公开(公告)号：US5008215A

    公开(公告)日：1991-04-16

    申请号：US377248

    申请日：1989-07-07

    申请人： Duen J. Chen ,  Guey F. Chi ,  Ying C. Yeh

    发明人： Duen J. Chen ,  Guey F. Chi ,  Ying C. Yeh

    IPC分类号： H01L43/10

    CPC分类号： H01L43/10 ,  Y10S148/003 ,  Y10S148/005 ,  Y10S148/118 ,  Y10S148/152

    摘要： A process for preparing high sensitivity indium antimonide film magnetoresistance element. A silicon single crystal wafer is treated with oxidative diffusion to form a layer of silicon oxide on the surface of the silicon single crystal, a layer of indium antimonide is grown on the substrate by vapor deposition, and the indium antimonide layer is then subjected to a specific annealing treatment in which the indium antimonide layer is partially oxidized and then re-crystallized. The resultant magnetoresistance element possessing improved sensitivity, stability and suitable for large scale production is obtained.

    摘要翻译： 制备高灵敏度锑锑薄膜磁阻元件的方法。 通过氧化扩散处理硅单晶晶片，以在硅单晶的表面上形成氧化硅层，通过气相沉积在衬底上生长锑化铟层，然后将铟锑化物层 其中锑化铟层被部分氧化然后再结晶的特定退火处理。 获得了具有提高的灵敏度，稳定性并且适合于大规模生产的所得磁阻元件。

    Ultra-thin semiconductor membranes
    16.
    发明授权
    Ultra-thin semiconductor membranes 失效
    超薄半导体膜

    公开(公告)号：US4946735A

    公开(公告)日：1990-08-07

    申请号：US284821

    申请日：1988-12-14

    申请人： Kevin C. Lee ,  Charles A. Lee ,  John Silcox

    发明人： Kevin C. Lee ,  Charles A. Lee ,  John Silcox

    IPC分类号： H01L21/3063 ,  H01L21/324 ,  H01L21/465 ,  H01L21/477

    CPC分类号： H01L21/3063 ,  H01L21/30635 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/465 ,  H01L21/477 ,  Y10S148/003 ,  Y10S148/005 ,  Y10S148/042 ,  Y10S148/056 ,  Y10S148/058 ,  Y10S148/064 ,  Y10S148/065 ,  Y10S148/083 ,  Y10S148/119 ,  Y10S148/135 ,  Y10S148/90 ,  Y10S438/924 ,  Y10S438/977 ,  Y10T428/261 ,  Y10T428/266 ,  Y10T428/31 ,  Y10T428/315

    摘要： This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium aresenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer. Thus, when the partially damaged semiconductor material is exposed to an etchant the etching rate in the damaged region is decreased by a factor of several thousand as compared to the undamagGOVERNMENT FUNDINGThe invention described and claimed herein was at least in part supported by the National Submicron Facility under NSF Grant #ECS-8200312 to the NRRFSS.

    摘要翻译： 本发明涉及可以由半导体材料如硅，锗和砷化镓形成的亚微米范围的超薄半导体膜。 通过低剂量离子注入在半导体的膜（例如，晶片）的抛光反面上形成薄的稍微损伤的表面，然后蚀刻膜前侧的半导体材料以除去半导体， 材料下降到离子植入损伤层。 虽然注入的离子可以从功能上需要的离子中选择，当退火保留在膜中以改变原始电特性时，也可以选择注入的离子，使得在退火时，所得的超薄半导体膜具有与 原来的半导体材料。 离子注入改变离子注入层的蚀刻特性。 因此，当部分损坏的半导体材料暴露于蚀刻剂时，与未损坏的半导体材料相比，损伤区域中的蚀刻速率降低了几千倍。

    Open-tube, benign-environment annealing method for compound semiconductors
    17.
    发明授权
    Open-tube, benign-environment annealing method for compound semiconductors 失效
    复合半导体的开放式，良性环境退火方法

    公开(公告)号：US4898834A

    公开(公告)日：1990-02-06

    申请号：US211839

    申请日：1988-06-27

    申请人： Arthur H. Lockwood ,  Adela Gonzales

    发明人： Arthur H. Lockwood ,  Adela Gonzales

    IPC分类号： H01L21/324 ,  H01L31/103 ,  H01L31/18

    CPC分类号： H01L21/3245 ,  H01L31/1035 ,  H01L31/1864 ,  Y02E10/50 ,  Y10S148/003 ,  Y10S148/005 ,  Y10S148/022 ,  Y10S148/084

    摘要： An improved system and method for annealing indium antimonide ion implanted junctions employing an open-tube benign annealing environment. A furnace having a hollow chamber therein is maintained continuously at a predetermined annealing temperature and wafers of indium antimonide to be annealed are inserted into the chamber through a resealable airlock at one end of the chamber. A source of molten indium saturated with antimony is provided within the chamber to maintain desired partial pressures of indium and antimony within the chamber. Hydrogen gas is continuously flushed through the chamber to purge contaminants and maintain the chamber at a desired slight overpressure over atmospheric. At the conclusion of annealing, the indium antimonide wafer is removed from the chamber into the airlock which is flushed with hydrogen gas. The wafer is allowed to cool to room temperature and removed from the airlock for subsequent processing steps.

    摘要翻译： 使用开放管良性退火环境退火铟锑离子注入接头的改进的系统和方法。 在其中具有中空室的炉子在预定的退火温度下连续地保持，并且待退火的锑化锑的晶片通过室的一端处的可重新密封的气闸插入室中。 在室内提供饱和锑的熔融源，以保持腔室内所需的铟和锑分压。 氢气不断冲洗通过室以清除污染物并将室维持在大气压下所需的轻微过压。 在退火结束时，将锑化铟晶片从室中移出到用氢气冲洗的气闸中。 将晶片冷却至室温，并从气闸中取出以用于随后的处理步骤。

    Intermetallic compound semiconductor thin film and method of manufacturing same
    18.
    发明授权
    Intermetallic compound semiconductor thin film and method of manufacturing same 失效
    金属间化合物半导体薄膜及其制造方法

    公开(公告)号：US4874438A

    公开(公告)日：1989-10-17

    申请号：US138192

    申请日：1987-11-30

    申请人： Masahide Oshita ,  Masaaki Isai ,  Toshiaki Fukunaka

    发明人： Masahide Oshita ,  Masaaki Isai ,  Toshiaki Fukunaka

    IPC分类号： H01L21/203 ,  H01L43/12 ,  H01L43/14

    CPC分类号： H01L43/12 ,  H01L21/0242 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02661 ,  H01L43/14 ,  Y10S148/005 ,  Y10S148/065 ,  Y10S148/169 ,  Y10S438/971

    摘要： An intermetallic compound semiconductor thin film comprises a single crystalline deposition thin film made of a III-V group intermetallic compound having a stoichiometry composition ratio of 1:1. When forming the III-V group semiconductor thin film by an evaporation method, a substrate temperature is initially maintained at a high level while the evaporation source temperature is gradually raised, and when the intermetallic composition of the III-V group begins to deposit on the substrate, the substrate temperature is lowered while the evaporation source temperature is maintained at the same level as existed at the time when the intermetallic compound is deposited, and the deposition time is controlled.

    摘要翻译： PCT No.PCT / JP87 / 00205 Sec。 371日期1987年11月30日 102（e）1987年11月30日PCT 1987年4月1日提交PCT。金属间化合物半导体薄膜包括由化学计量组成比为1:1的III-V族金属间化合物制成的单晶沉积薄膜。 当通过蒸发法形成III-V族半导体薄膜时，基板温度最初保持在高水平，同时蒸发源温度逐渐升高，并且当III-V族金属间化合物开始沉积在 衬底时，衬底温度降低，同时蒸发源温度保持在金属间化合物沉积时存在的相同水平，并且控制沉积时间。