公开(公告)号：US5196360A

公开(公告)日：1993-03-23

申请号：US866093

申请日：1992-04-06

申请人： Trung T. Doan ,  Gurtej S. Sandhu

发明人： Trung T. Doan ,  Gurtej S. Sandhu

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  Y10S148/015 ,  Y10S148/019

摘要： The present invention is directed to methods for preparing silicide contact areas on integrated circuit devices which inhibit outgrowth of silicide and formation of potential short circuit paths between adjacent silicide contact areas. This may be achieved by depositing a nitrogen-rich titanium nitride layer over the conventional titanium layer prior to silicidation. In those regions on the integrated circuit device where titanium is deposited on spacer oxide regions separating adjacent silicide contact areas, excess nitrogen from the nitrogen-rich titanium nitride layer reacts with the titanium film to form titanium nitride. The final structure after silicidation contains titanium silicide contact areas separated by titanium nitride regions. The titanium nitride regions inhibit outgrowth of titanium silicide from the silicide contact areas. After silicidation, excess titanium nitride and titanium may be removed by etching.

摘要翻译： 本发明涉及在集成电路器件上制备硅化物接触区域的方法，该方法抑制硅化物的生长并形成相邻的硅化物接触区域之间的潜在的短路路径。 这可以通过在硅化之前在常规钛层上沉积富氮氮化钛层来实现。 在分离相邻硅化物接触区域的间隔氧化物区域上沉积钛的集成电路器件的那些区域中，来自富氮氮化钛层的过量氮与钛膜反应形成氮化钛。 硅化后的最终结构包含由氮化钛区域分离的硅化钛接触区域。 氮化钛区域从硅化物接触区域抑制硅化钛的生长。 在硅化后，可以通过蚀刻除去过量的氮化钛和钛。

公开(公告)号：US5132237A

公开(公告)日：1992-07-21

申请号：US647494

申请日：1991-01-28

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC分类号： H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

摘要： A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required for the interconnection of the MOS and NPN transistors.

公开(公告)号：US5081065A

公开(公告)日：1992-01-14

申请号：US621116

申请日：1990-11-30

申请人： Alexander G. M. Jonkers ,  Christopher A. Seams ,  Harald Godon ,  Andre Stolmeijer

发明人： Alexander G. M. Jonkers ,  Christopher A. Seams ,  Harald Godon ,  Andre Stolmeijer

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L21/76895 ,  H01L21/28518 ,  Y10S148/019

摘要： Disclosed is a method of contacting a metal silicide pattern on an integrated semiconductor circuit which is provided with a planarized dielectric layer. A silicide-forming metal layer (9), preferably a titanium layer, is provided on the surface of a silicon substrate having a field oxide patter (2) which is provided with a conductor pattern (4) of silicon. A layer (10) of amorphous (a-) silicon is provided locally on this metal layer to form "straps". The entire device is heated in a nitrogen-containing atmosphere, by which the metal layer (9) is converted at least partly into metal silicide (12). A dielectric layer (13), for example of silicon oxide, is provided over the entire surface. The layer (13) is planarized and provided with contact windows (15) on the metal silicide by etching, after which a metallization (16) is provided. According to the invention, the amorphous silicon layer is provided not only at the locations of the "straps", but also under at least those contact windows which are situated above the silicon pattern (4), and preferably below all contact windows, so that a thicker silicide layer (12B) is realized below these windows and partial or substantial removal by etching of the metal silicide in the "shallow" contact windows is prevented.

公开(公告)号：US5066613A

公开(公告)日：1991-11-19

申请号：US380175

申请日：1989-07-13

申请人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

发明人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

IPC分类号： H01L21/768 ,  H01L21/86 ,  H01L23/482

CPC分类号： H01L23/4825 ,  H01L21/76889 ,  H01L21/86 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/147

摘要： A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

摘要翻译： 在绝缘基板上形成的集成电路半导体器件之间形成导电互连区域的工艺利用半导体材料本身形成器件互连区域。 半导体材料的图案层直接形成在绝缘基板的表面上。 图案化层包括要形成半导体器件的区域以及用于互连预定半导体器件的端子的区域。 在半导体材料的选定区域中形成半导体器件之后，图案化成互连的半导体材料的区域被转换为半导体材料的金属化合物。

公开(公告)号：US4983531A

公开(公告)日：1991-01-08

申请号：US478390

申请日：1990-02-12

申请人： Stephen J. Cosentino

发明人： Stephen J. Cosentino

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8249

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/8249 ,  H01L29/66272 ,  Y10S148/019 ,  Y10S148/123

摘要： An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer over a thin silicon dioxide layer combined with a polysilicon layer. This bipolar structure has a self-aligned, P-type extrinsic base which results in lower base resistance and improved performance.

摘要翻译： 通过在与多晶硅层结合的薄二氧化硅层上利用氮化物层来制造BiCMOS集成电路的改进的双极晶体管。 该双极结构具有自对准的P型外部碱，导致较低的耐碱性和改进的性能。

公开(公告)号：US4886765A

公开(公告)日：1989-12-12

申请号：US262773

申请日：1988-10-26

申请人： Min-Liang Chen ,  Chung W. Leung ,  Chih-Yuan Lu ,  Nun-Sian Tsai

发明人： Min-Liang Chen ,  Chung W. Leung ,  Chih-Yuan Lu ,  Nun-Sian Tsai

IPC分类号： H01L21/28 ,  H01L21/3105

CPC分类号： H01L21/3105 ,  H01L21/28052 ,  Y10S148/017 ,  Y10S148/019 ,  Y10S438/906 ,  Y10S438/909

摘要： Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.

摘要翻译： 硅胶对亚微米VLSIC技术很重要。 在通过简单地沉积金属膜并加热该金属以形成硅化物层的已知技术来形成硅化物中已经发现了问题。 本发明解决了这些问题，通过识别聚合物污染物可以从通常使用的先前的反应离子蚀刻步骤留在表面上，并且通过在低温下在干燥氧气中加热的附加步骤来除去金属沉积物中的任何这样的污染物，例如 800摄氏度之前，污染已经显着硬化。

公开(公告)号：US4883772A

公开(公告)日：1989-11-28

申请号：US241784

申请日：1988-09-06

申请人： James M. Cleeves ,  James G. Heard

发明人： James M. Cleeves ,  James G. Heard

IPC分类号： H01L21/285 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/1004 ,  H01L21/28518 ,  H01L29/42304 ,  H01L29/456 ,  Y10S148/019 ,  Y10S148/105

摘要： A silicide base shunt 50 and method of fabricating it are disclosed for a bipolar transistor. The base shunt 50 is fabricated using the first layer metal 36, 39 as a mask to etch silicon dioxide 27 surrounding the emitter 34 to thereby expose the underlying silicon epitaxial layer 24. Nickel or copper are then deposited onto the silicon 24 to form a region of silicide 50 extending from a base contact 36 to closely proximate the emitter 34, thereby minimizing the resistance of the extrinsic base region 24 of the transistor.

摘要翻译： 公开了一种用于双极晶体管的硅化物基极分路器50及其制造方法。 使用第一层金属36,39作为掩模来制造基极分路器50，以蚀刻围绕发射极34的二氧化硅27，从而暴露下面的硅外延层24.然后将镍或铜沉积到硅24上以形成区域 的硅化物50从基极触点36延伸到靠近发射极34的位置，由此最小化晶体管的外部基极区域24的电阻。

公开(公告)号：US4714951A

公开(公告)日：1987-12-22

申请号：US833845

申请日：1986-02-26

申请人： Annie Baudrant ,  Michel Marty

发明人： Annie Baudrant ,  Michel Marty

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/45 ,  H01L29/78 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/31683 ,  H01L29/456 ,  H01L29/665 ,  Y10S148/019 ,  Y10S148/02 ,  Y10S148/117 ,  Y10S148/147

摘要： The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi.sub.2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta.sub.2 O.sub.5, especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.

摘要翻译： 本发明涉及一种单晶或多晶硅区域的集成电路，其中源极，栅极和漏极由硅化钽TaSi 2覆盖，而其余部分被部分氧化钽Ta 2 O 5的一部分覆盖，特别是在 多晶硅的栅极和厚氧化物和铝合金层与硅化钽接触形成与硅化钽的部分的连接。

公开(公告)号：US4586968A

公开(公告)日：1986-05-06

申请号：US628408

申请日：1984-07-06

申请人： Augustin Coello-Vera

发明人： Augustin Coello-Vera

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/60 ,  H01L29/41 ,  H01L29/732 ,  H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/2257 ,  H01L29/41 ,  H01L29/66303 ,  Y10S148/019 ,  Y10S148/02 ,  Y10S148/106 ,  Y10S148/151

摘要： Apart from the base fingers (10), this transistor includes a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating (4). The edges of sandwiches made up of bands (3) and (4) are bordered by a silica bank (7) formed automatically by deposit and anisotropic attack, without additional masking. The emitter fingers (9) are overhung by a polycrystalline silicon layer (8) from which doping of these fingers has been obtained.The possibility is also obtained, automatically and without masks alignment, of having the emitter and base fingers brought firmly together with minimum protection distances.

摘要翻译： 除了基底指（10）之外，该晶体管还包括已形成基极扩散的硅化钛涂层和氮化硅涂层（4）。 由条带（3）和（4）组成的三明治边缘是由沉积和各向异性攻击自动形成的二氧化硅银（7）边界，无需额外掩蔽。 发射极指（9）被多晶硅层（8）覆盖，从中可以获得这些指状物的掺杂。 也可以自动地且没有掩模对准的可能性，使发射器和基部手指以最小的保护距离牢固地连接在一起。

公开(公告)号：US4271424A

公开(公告)日：1981-06-02

申请号：US146220

申请日：1980-05-05

申请人： Katsuyuki Inayoshi ,  Kazutoshi Miyao

发明人： Katsuyuki Inayoshi ,  Kazutoshi Miyao

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L23/057 ,  H01L27/088 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/45 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62

CPC分类号： H01L23/057 ,  H01L21/2855 ,  H01L27/088 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/456 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/01079 ,  H01L2924/16195 ,  Y10S148/019 ,  Y10S148/02 ,  Y10S148/055 ,  Y10S148/122 ,  Y10S148/147 ,  Y10S257/902 ,  Y10S257/914

摘要： Disclosed herein is an improvement for the electrode structure of the MIS type semiconductor integrated circuit, in which the ohmic contact with the Si substrate is formed on the top of the semiconductor chip. The electrodes which consist of an upper Al layer and a lower polycrystalline Si layer are used for a drain electrode and a source electrode. These electrodes should be isolated from the substrate by the underlying PN junction. Another electrode, for connecting to the substrate consists of an Al layer directly in contact with the underlying N type region and which is short circuited with the substrate through the N type region due to the alloy formation between the Al and the substrate material. An MIS type semiconductor device with a grounded substrate or with a back gate bias is obtained in a simple structure by the improved source and drain electrode structure.

摘要翻译： 这里公开了MIS半导体集成电路的电极结构的改进，其中在半导体芯片的顶部上形成与Si衬底的欧姆接触。 由上部Al层和下部多晶Si层构成的电极用于漏电极和源电极。 这些电极应通过下面的PN结与衬底隔离。 用于连接到衬底的另一个电极由直接与下面的N型区域接触的Al层组成，并且由于Al和衬底材料之间的合金形成而与衬底通过N型区域短路。 通过改进的源极和漏极结构，以简单的结构获得具有接地衬底或背栅偏压的MIS型半导体器件。