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公开(公告)号：US20230083850A1
公开(公告)日：2023-03-16
申请号：US17802122
申请日：2021-01-31
申请人： 7Tunnels Inc.
发明人： Michael David Adams
摘要： Systems and methods include a random number pool in communication with a random number device. One or more sets of key data elements are developed using the random number device with one or more variables input into the random number device from the random number pool.
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公开(公告)号：US11606695B2
公开(公告)日：2023-03-14
申请号：US16485486
申请日：2018-02-27
IPC分类号： H04W12/50 , H04W76/14 , H04W76/11 , G08B5/36 , H04L9/08 , H04W4/80 , G05B19/042 , G08C17/02 , H01H71/04 , H02H1/00 , H04L67/00 , G01R31/74 , H02H3/10 , H02H7/26 , H04L12/28 , G01R31/327 , G05B13/02 , G06F8/65 , H04Q9/00 , H04W12/03 , H04W12/0471 , G06F7/58
摘要： Communication enabled circuit breakers are described. Methods associated with such communication enabled circuit breakers are also described. The communication enabled circuit breakers may include one or more current sensors. The one or more current sensors may be disposed in a clip. The clip may be coupled to a line side phase connection, and the clip may be shielded to attenuate signals.
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公开(公告)号：US11601053B2
公开(公告)日：2023-03-07
申请号：US16712693
申请日：2019-12-12
发明人： Joerg Erik Goller
摘要： An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.
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公开(公告)号：US11599272B2
公开(公告)日：2023-03-07
申请号：US17348226
申请日：2021-06-15
发明人： Zhenming Zhou , Seungjune Jeon , Zhenlei Shen
摘要： Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.
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公开(公告)号：US20230067363A1
公开(公告)日：2023-03-02
申请号：US17441801
申请日：2021-06-17
发明人： Xian FAN
摘要： The embodiments of the present disclosure provide a random number generation circuit, including: a random number generator, including a feedback module and a plurality of sequentially connected flip-flops, where an output terminal of a previous flip-flop being connected to an input terminal of a next flip-flop, the output terminal of each of the flip-flops serving as an output terminal of the random number generator, and an output terminal of the feedback module being connected to the input terminal of one of the flip-flops; the feedback module being configured to receive selection signals and select, on the basis of the selection signals, the output terminals of two of the flip-flops as input terminals of the feedback module; and the random number generator being configured to output a plurality of first random numbers corresponding to corresponding selection signals in each counting cycle.
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公开(公告)号：US20230065911A1
公开(公告)日：2023-03-02
申请号：US17462354
申请日：2021-08-31
发明人： Gregory A. Kemp
IPC分类号： G06F11/263 , G06F7/58 , G06F1/04
摘要： A test stimulus generator generates error irritations, or error sequences, within a processor system. The test stimulus generator includes an initialization register, a pseudorandom number generator (PRNG), a clock subsystem, and an output register. The PRNG calculates an output value from an initialization value stored in the initialization register. The PRNG output value represents a unique error irritation and identifies one or more components within the processor system to handle the error irritation. The clock subsystem generates either a continuous or pulsed clock signal that transfers the initialization value into the PRNG. The output register stores the PRNG output value and transmits the corresponding error irritation to the processor components identified to handle the error irritation. The test stimulus generator generates error irritations in a predetermined or random order based on the initialization value. A corresponding method and computer program product are also disclosed.
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公开(公告)号：US20230065643A1
公开(公告)日：2023-03-02
申请号：US17464387
申请日：2021-09-01
发明人： Cruz VARGAS , Bryant YEE , Sarah OLSEN
摘要： Embodiments are directed to systems and techniques to generate random numbers via contactless cards.
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公开(公告)号：US20230058013A1
公开(公告)日：2023-02-23
申请号：US17978525
申请日：2022-11-01
申请人： FortifID, Inc.
发明人： Anirban Basak , Thomas P. Hardjono
IPC分类号： H04L67/06 , G16H10/60 , H04L67/1097 , G06F7/58 , H04L9/32
摘要： Techniques are described for algorithmic confidential computing on personal data and to an insights provider providing access to personal data using limited-use anonymous insights records stored on a blockchain. To enable service providers and other queriers to obtain such insights information in a secure manner, an insights provider creates an anonymous insights record that is recorded on a blockchain responsive a request from a subject indicating that the subject desires to share one or more items of insights information. An anonymous insights record contains a single-use (or limited number of use) random number that is used by the insights provider to index the data in a shards index database for the relevant shards of the insights data file. These multiple segments can then be stored across multiple separate repositories using a decentralized file storage service.
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公开(公告)号：US11586743B2
公开(公告)日：2023-02-21
申请号：US16362057
申请日：2019-03-22
申请人： Via Science, Inc.
IPC分类号： G06F21/60 , G06F11/34 , G06N3/10 , G06F7/58 , G06N3/04 , H04L9/00 , H04L9/30 , G06N20/10 , G06Q20/38 , G06F21/62 , G06N3/084
摘要： A first system creates and sends encryption key data to multiple data sources. A second system receives data encrypted using the encryption key data from the multiple data sources; the data may include noise data such that, even if decrypted, the original data cannot be discovered. Because the encryption is additively homomorphic, the second system may create encrypted summation data using the encrypted data. The first system separately receives the noise data encrypted using the same technique as the encrypted data. The second system may send the encrypted summation data to the first system, which may then remove the noise data from the encrypted summation data to create unencrypted summation data.
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公开(公告)号：US11586560B2
公开(公告)日：2023-02-21
申请号：US17165361
申请日：2021-02-02
申请人： Intel Corporation
发明人： Rodrigo R. Branco , Shay Gueron
摘要： Various examples are directed to systems and methods for securing a data storage device. A storage controller may receive a read request directed to the data storage device. The read request may comprise address data indicating a first address of a first storage location at the data storage device. The storage controller may request from the data storage device a first encrypted data unit stored at the first memory element and a first encrypted set of parity bits, such as Error Correction Code (ECC) bits, associated with the first storage location. An encryption system may decrypt the first encrypted set of parity bits to generate a first set of parity bits based at least in part on an a first location parity key for the first address.
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