公开(公告)号：US11343548B2

公开(公告)日：2022-05-24

申请号：US16402422

申请日：2019-05-03

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody

IPC: H04N19/12 ,  H04N21/2343 ,  H04N19/136

Abstract: Several systems and methods for processing of video frames based on one or more video formats are disclosed. In an embodiment, a video processing system comprises a memory and a video engine. The memory stores a plurality of video frames, a primary set of instructions and a plurality of secondary sets of processing instructions. Each secondary set of processing instructions is associated with a video format. The video engine is loaded with the primary set of instructions and is configured to fetch one or more video frames and a secondary set of processing instructions from the memory based on the loaded primary set of instructions. The fetched secondary set of processing instructions corresponds to a video format determined for processing of the one or more video frames. The video engine performs processing of the one or more video frames based on the secondary set of processing instructions.

公开(公告)号：US11341606B2

公开(公告)日：2022-05-24

申请号：US16930543

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06K9/32 ,  G06T3/40 ,  G06T1/20 ,  H04N1/393

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.

公开(公告)号：US20220012115A1

公开(公告)日：2022-01-13

申请号：US17483713

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Manoj Koul

IPC: G06F11/07 ,  G06K9/62 ,  G06T5/00 ,  G06K9/56 ,  G06K9/03

Abstract: Methods, apparatus, and articles of manufacture providing an efficient safety mechanism for signal processing hardware are disclosed. An example apparatus includes an input interface to receive an input signal; a hardware accelerator to process the input signal, the hardware accelerator including: unprotected memory to store non-critical data corresponding to the input signal; and protected memory to store critical data corresponding to the input signal; and an output interface to transmit the processed input signal.

公开(公告)号：US20210337242A1

公开(公告)日：2021-10-28

申请号：US17367387

申请日：2021-07-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Chaitanya S. Ghone ,  Joseph Meehan

IPC: H04N19/86 ,  H04N19/82 ,  H04N19/42 ,  H04N19/44

Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.

公开(公告)号：US11157345B2

公开(公告)日：2021-10-26

申请号：US15844170

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Manoj Koul

IPC: G06F11/07 ,  G06K9/62 ,  G06T5/00 ,  G06K9/56 ,  G06K9/03 ,  G06T7/00 ,  H04L12/24

Abstract: Methods, apparatus, and articles of manufacture providing an efficient safety mechanism for signal processing hardware are disclosed. An example apparatus includes an input interface to receive an input signal; a hardware accelerator to process the input signal, the hardware accelerator including: unprotected memory to store non-critical data corresponding to the input signal; and protected memory to store critical data corresponding to the input signal; and an output interface to transmit the processed input signal.

公开(公告)号：US20210311782A1

公开(公告)日：2021-10-07

申请号：US17349310

申请日：2021-06-16

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, JR. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US20210281862A1

公开(公告)日：2021-09-09

申请号：US17330840

申请日：2021-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/117

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US11068308B2

公开(公告)日：2021-07-20

申请号：US16298709

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Jesse Gregory Villarreal, Jr. ,  Lucas Carl Weaver ,  Brijesh Jadav ,  Niraj Nandan

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

公开(公告)号：US20210117254A1

公开(公告)日：2021-04-22

申请号：US17138036

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US20210103465A1

公开(公告)日：2021-04-08

申请号：US17123653

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task sched