公开(公告)号：US11546598B2

公开(公告)日：2023-01-03

申请号：US17865119

申请日：2022-07-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/169

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

公开(公告)号：US11546590B2

公开(公告)日：2023-01-03

申请号：US17582937

申请日：2022-01-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei Sun ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component, and clips the second coefficient value. The circuitry generates a third coefficient value by adding the first coefficient value to the clipped second coefficient value, and clips the third coefficient value. The circuitry encodes a third reconstructed image sample of the chroma component using the clipped third coefficient value.

公开(公告)号：US11533482B2

公开(公告)日：2022-12-20

申请号：US17306483

申请日：2021-05-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Sughosh Pavan Shashidhar ,  Ru Ling Liao ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/176

Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.

公开(公告)号：US11490093B2

公开(公告)日：2022-11-01

申请号：US17190920

申请日：2021-03-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/52 ,  H04N19/513 ,  H04N19/137 ,  H04N19/105 ,  H04N19/176 ,  H04N19/159

Abstract: Provided is an encoder including circuitry and memory. In operation, the circuitry: derives one or more first motion vectors based on at least one of one or more motion vectors of a first block encoded in an affine mode; derives one or more second motion vectors based on at least one of one or more motion vectors of a second block that has been encoded and is different from the first block; and determines, as motion vector predictors at control points of a current block to be encoded, motion vectors including at least one of the first motion vectors and at least one of the second motion vectors.

公开(公告)号：US11438621B2

公开(公告)日：2022-09-06

申请号：US17087904

申请日：2020-11-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Ru Ling Liao ,  Jing Ya Li ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/52

Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.

公开(公告)号：US11425409B2

公开(公告)日：2022-08-23

申请号：US17130298

申请日：2020-12-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi Hashimoto ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/513 ,  H04N19/105 ,  H04N19/176

Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US11410552B2

公开(公告)日：2022-08-09

申请号：US16283200

申请日：2019-02-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Toshiyasu Sugio ,  Toru Matsunobu ,  Satoshi Yoshikawa ,  Tatsuya Koyama

IPC: G08G1/0968 ,  B60W30/182 ,  G08G1/09 ,  G05D1/02 ,  G01C21/28 ,  G01S19/01 ,  G06V20/10 ,  B60W50/00 ,  B60W50/10 ,  B60W50/14 ,  G01C21/32 ,  G01C21/36

Abstract: A three-dimensional information processing method includes: obtaining, via a communication channel, map data that includes first three-dimensional position information; generating second three-dimensional position information from information detected by a sensor; judging whether one of the first three-dimensional position information and the second three-dimensional position information is abnormal by performing, on one of the first three-dimensional position information and the second three-dimensional position information, a process of judging whether an abnormality is present; determining a coping operation to cope with the abnormality when one of the first three-dimensional position information and the second three-dimensional position information is judged to be abnormal; and executing a control that is required to perform the coping operation.

公开(公告)号：US11368709B2

公开(公告)日：2022-06-21

申请号：US16801797

申请日：2020-02-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/593 ,  H04N19/157 ,  H04N19/105 ,  H04N19/513 ,  H04N19/176 ,  H04N19/182 ,  H04N19/196

Abstract: An encoder is an encoder that encodes a block in a picture using a prediction image of the block, and includes circuitry and memory. Using the memory, the circuitry: calculates a first average pixel value which is an average pixel value of first reference samples out of the first reference samples and second reference samples, The first reference samples are referable and located outside the block and adjacent to a first side of the block. The second reference samples are referable and located outside the block and adjacent to a second side of the block. When generating the prediction image, the circuitry applies the same prediction pixel value to inner samples among current samples to be processed that are included in the block. The inner samples constitute a quadrilateral region including at least two current samples in each of a horizontal direction and a vertical direction.

公开(公告)号：US11368686B2

公开(公告)日：2022-06-21

申请号：US17194781

申请日：2021-03-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe

IPC: H04N19/105 ,  H04N19/117 ,  H04N19/82 ,  H04N19/52 ,  H04N19/174 ,  H04N19/119 ,  H04N19/159

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: splits one picture included in pictures into areas, intra encodes the entirety of an area among the areas; and switches areas to be intra encoded for each picture included in the pictures. In at least one of (i) generation of a reference pixel in inter prediction or (ii) loop filtering, only pixels in the area intra encoded or pixels in an area which precedes the area intra encoded in coding order are used among pixels included in the pictures.

公开(公告)号：US11350091B2

公开(公告)日：2022-05-31

申请号：US16833174

申请日：2020-03-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Ru Ling Liao ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/50 ,  H04N19/60

Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.