公开(公告)号：US07990245B1

公开(公告)日：2011-08-02

申请号：US12765548

申请日：2010-04-22

申请人： Igor Krichtafovitch

发明人： Igor Krichtafovitch

IPC分类号： H01F27/30

CPC分类号： H01F27/325 ,  H01F2005/022

摘要： Improved multi-sectional bobbin designs described herein define a channel suitable to accommodate a portion of the wire that transits from prior winding section to the next, wherein opposing walls of the channel so defined separate the transiting portion of the wire from both prior and next winding sections through a substantial entirety of the wires descent from an upper winding layer in the prior section to a lower winding layer in the next.

摘要翻译： 本文所述的改进的多节段筒管设计限定了适于容纳从现有卷绕部分转移到下一个卷绕部分的部分的通道的通道，其中如此限定的通道的相对壁将先前和下一个绕组的过渡部分分开 通过从前一部分的上部卷绕层下降到下一个下部卷绕层的大部分整体的部分。

公开(公告)号：US07978492B2

公开(公告)日：2011-07-12

申请号：US12725269

申请日：2010-03-16

申请人： Mark G. Johnson ,  Thomas H. Lee ,  James M. Cleeves

发明人： Mark G. Johnson ,  Thomas H. Lee ,  James M. Cleeves

IPC分类号： G11C5/06

CPC分类号： G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：US07948222B2

公开(公告)日：2011-05-24

申请号：US12366233

申请日：2009-02-05

申请人： Peter Thomas Hardman ,  Erwin Pang ,  Sanjiv K. Lakhanpal

发明人： Peter Thomas Hardman ,  Erwin Pang ,  Sanjiv K. Lakhanpal

IPC分类号： G05F1/00

CPC分类号： H02M3/1584 ,  H02M3/1588 ,  H02M2003/1586 ,  Y02B70/1466

摘要： Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

摘要翻译： 用于在开关模式转换器电路中执行DC至DC功率转换的技术包括动态开关切换，相位脱落，对称相位电路拓扑和非对称相位电路拓扑的组合。 在本发明的至少一个实施例中，一种操作功率转换器电路的方法包括当功率转换器电路被配置为第一操作模式时，使用第一数量的开关器件操作第一相位开关电路部分。 第一个数字大于零。 该方法包括当功率转换器电路被配置为第二操作模式时，使用第一数量的开关器件来操作第一相位开关电路部分。 该方法包括当功率转换器电路被配置为第二操作模式时，使用第二数量的开关装置来操作第二相位开关电路部分。 第二个数字大于第一个数字。

公开(公告)号：US07929515B2

公开(公告)日：2011-04-19

申请号：US12337915

申请日：2008-12-18

申请人： Sarat Puthenpura ,  David G. Belanger ,  Sam Parker ,  Wenjie Zhao ,  Arun Jotshi

发明人： Sarat Puthenpura ,  David G. Belanger ,  Sam Parker ,  Wenjie Zhao ,  Arun Jotshi

IPC分类号： H04L12/28 ,  H04W4/00 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L41/145 ,  H04W16/18

摘要： A technique for reducing costs associated with a radio access network of a mobile telecommunications network includes configuring the radio access network using a linear programming model of the radio access network subject to constraints. The technique includes selecting cellular sites and hub locations of the radio access network to be connected by broadband wireless links based on the linear programming model and constraints. In at least one embodiment of the invention, a method of designing a radio access network of links between a cellular site and a core network includes selecting at least one first link of the radio access network to be at least one first wireless link at least partially based on a linear programming model of the radio access network. The method includes configuring an output device of a computer system to indicate the selection.

摘要翻译： 用于降低与移动电信网络的无线电接入网络相关联的成本的技术包括使用经受约束的无线电接入网络的线性规划模型来配置无线电接入网络。 该技术包括基于线性规划模型和约束来选择要由宽带无线链路连接的无线电接入网络的蜂窝站点和集线器位置。 在本发明的至少一个实施例中，设计蜂窝站点和核心网络之间的链路的无线电接入网络的方法包括：选择至少一个第一无线链路至少一个第一无线链路至少部分地 基于无线电接入网络的线性规划模型。 该方法包括配置计算机系统的输出设备以指示选择。

公开(公告)号：US07916806B2

公开(公告)日：2011-03-29

申请号：US11828790

申请日：2007-07-26

申请人： Siavash Alamouti ,  Vahid Tarokh

发明人： Siavash Alamouti ,  Vahid Tarokh

IPC分类号： H04L27/00

CPC分类号： H04B7/0857 ,  H04B1/02 ,  H04B7/0613 ,  H04B7/0615 ,  H04B7/0667 ,  H04B7/0669 ,  H04B7/0671 ,  H04B7/0689 ,  H04B7/0837 ,  H04B7/0845 ,  H04B7/0854 ,  H04B7/0891 ,  H04B7/12 ,  H04L1/0054 ,  H04L1/04 ,  H04L1/0606 ,  H04L1/0618 ,  H04L1/0625 ,  H04L1/0631 ,  H04L1/0643 ,  H04L1/0668 ,  H04L1/08 ,  H04L25/0202

摘要： A simple block coding arrangement is created with symbols transmitted over a plurality of transmit channels, in connection with coding that comprises only simple arithmetic operations, such as negation and conjugation. The diversity created by the transmitter utilizes space diversity and either time or frequency diversity. Space diversity is effected by redundantly transmitting over a plurality of antennas, time diversity is effected by redundantly transmitting at different times, and frequency diversity is effected by redundantly transmitting at different frequencies: Illustratively, using two transmit antennas and a single receive antenna, one of the disclosed embodiments provides the same diversity gain as the maximal-ratio receiver combining (MRRC) scheme with one transmit antenna and two receive antennas. The principles of this invention are applicable to arrangements with more than two antennas, and an illustrative embodiment is disclosed using the same space block code with two transmit and two receive antennas.

摘要翻译： 结合仅包括诸如否定和共轭的简单算术运算的编码，创建具有通过多个发送信道发送的符号的简单块编码布置。 发射机产生的分集利用空间分集和时间或频率分集。 通过在多个天线上进行冗余发送来实现空间分集，通过在不同时间进行冗余发送实现时间分集，并且通过以不同频率进行冗余传输来实现频率分集：说明性地，使用两个发射天线和单个接收天线 所公开的实施例提供与最大比率接收机组合（MRRC）方案与一个发射天线和两个接收天线相同的分集增益。 本发明的原理可应用于具有两个以上天线的布置，并且使用具有两个发射天线和两个接收天线的相同空间块码公开了一个说明性实施例。

公开(公告)号：US07913150B2

公开(公告)日：2011-03-22

申请号：US11685263

申请日：2007-03-13

申请人： Paul C. Miranda

发明人： Paul C. Miranda

IPC分类号： H03M13/00

CPC分类号： H03M13/091

摘要： An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.

摘要翻译： 可与多个数据传输协议一致操作的集成电路通信接口包括实现循环冗余校验（即CRC）功能的错误检测电路。 所述错误检测电路至少部分地基于所选择的多个数据传输协议之一生成校验和。 误差检测电路包括至少一个根据包括多个数据传输协议共同的术语的操作产生数字码的电路。 该数字代码与选定的数字代码组合以产生CRC。 所选择的数字码由与多个数据传输协议中的相应一个对应的单独电路产生。 单独电路根据包括多个数据传输协议中的相应一个专用的至少术语的操作来生成所选择的数字代码。

公开(公告)号：US07839225B2

公开(公告)日：2010-11-23

申请号：US12197516

申请日：2008-08-25

申请人： Yunteng Huang

发明人： Yunteng Huang

IPC分类号： H03B19/00 ,  H03L1/02 ,  H03L7/18

CPC分类号： H03L7/1976 ,  H03K5/1565 ,  H03L7/0992 ,  H03L7/18

摘要： A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.

摘要翻译： 时钟合成电路包括接收分频比并产生整数部分和数字量化误差（小数部分）的ΔΣ调制器。 分数N分频器根据对应于整数部分的除法控制值分割接收信号，并产生分频信号。 相位内插器根据数字量化误差来调整分频信号的相位，从而减小与分数N分频器相关联的噪声。

公开(公告)号：US07825708B2

公开(公告)日：2010-11-02

申请号：US12249457

申请日：2008-10-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

IPC分类号： H03L7/06

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

公开(公告)号：US07804138B2

公开(公告)日：2010-09-28

申请号：US11486347

申请日：2006-07-13

申请人： Wesley H. Morris

发明人： Wesley H. Morris

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/66477 ,  H01L21/761 ,  H01L23/552 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/1087 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

摘要翻译： 半导体器件可以使用常规设计和工艺制造，但包括专门的结构以减少或消除由各种形式的辐射引起的有害影响。 这样的半导体器件可以包括在本申请中公开的一个或多个寄生隔离器件和/或掩埋保护环结构。 适应这些新颖结构的设计和/或工艺步骤的引入与常规CMOS制造工艺兼容，因此可以以相对低的成本和相对简单的方式实现。

公开(公告)号：US07777585B1

公开(公告)日：2010-08-17

申请号：US12145647

申请日：2008-06-25

申请人： Jeffrey L. Sonntag

发明人： Jeffrey L. Sonntag

IPC分类号： H03L1/02

CPC分类号： H03L1/02 ,  H03B5/1206

摘要： A technique for reducing temperature sensitivity of an LC oscillator circuit includes a passive circuit coupled in parallel with a load capacitor. In at least one embodiment, an oscillator circuit is configured to generate a periodic signal having a free-running frequency. The oscillator circuit includes a first circuit portion including at least one inductor coupled in parallel with at least one load capacitor. The first circuit portion has an inductance-capacitance product that has a first temperature sensitivity. The oscillator circuit includes a passive circuit portion coupled in parallel with the first circuit portion. The passive circuit portion includes at least one resistor in series with at least one capacitor. The passive circuit portion has a second temperature sensitivity that opposes an effect of the first temperature sensitivity on the free-running frequency of the oscillator circuit, thereby reducing temperature sensitivity of the free-running frequency.

摘要翻译： 用于降低LC振荡器电路的温度灵敏度的技术包括与负载电容并联耦合的无源电路。 在至少一个实施例中，振荡器电路被配置为产生具有自由运行频率的周期信号。 振荡器电路包括第一电路部分，其包括与至少一个负载电容器并联耦合的至少一个电感器。 第一电路部分具有具有第一温度灵敏度的电感电容产品。 振荡器电路包括与第一电路部分并联耦合的无源电路部分。 无源电路部分包括与至少一个电容器串联的至少一个电阻器。 无源电路部分具有与第一温度灵敏度对振荡器电路的自由运行频率的影响相反的第二温度灵敏度，从而降低自由运行频率的温度灵敏度。