公开(公告)号：US20050251717A1

公开(公告)日：2005-11-10

申请号：US10842376

申请日：2004-05-10

申请人： Alon Saado ,  Muhammad Afsar

发明人： Alon Saado ,  Muhammad Afsar

IPC分类号： G01R31/28 ,  G06F11/00 ,  H03M13/00 ,  H04L1/00 ,  H04L1/20

CPC分类号： H04L1/0052 ,  H04L1/0061

摘要： The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

摘要翻译： 本发明涉及包括逻辑电路，比较电路，控制电路和存储器接口的装置。 逻辑电路可以被配置为响应于（i）具有一系列逻辑传输单元（LTU）的数据信号和（ii）第一控制信号而产生检查信号。 比较电路可以被配置为响应于检查信号和数据信号而产生比较信号。 所述控制电路经配置以响应于数据有效信号和所述比较信号产生（i）所述第一控制信号和（ii）指示每个所述LTU的有效或无效状态的第二控制信号。 存储器接口可以被配置为响应于第二控制信号而产生输出数据信号。 存储器接口通常被配置为仅存储具有有效状态的LTU。

公开(公告)号：US20050249204A1

公开(公告)日：2005-11-10

申请号：US10840492

申请日：2004-05-06

申请人： Alon Saado

发明人： Alon Saado

IPC分类号： H04L12/56 ,  H04L29/02

CPC分类号： G06F13/124

摘要： The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.

摘要翻译： 本发明涉及包括数据单元，存储器和控制单元的装置。 数据单元可以被配置为响应于包括一系列单词的输入信号来生成包括一系列帧的输出信号，每个帧具有报头和有效载荷。 存储器可以被配置为保持输出信号并与设备进行接口。 控制单元可以被配置为呈现配置成控制数据单元和存储器的一个或多个控制信号。

公开(公告)号：US20050220151A1

公开(公告)日：2005-10-06

申请号：US10812810

申请日：2004-03-30

申请人： Alon Saado

发明人： Alon Saado

IPC分类号： G06F5/01 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0605 ,  H04L7/0008

摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data output signal in response to a data input signal, a valid word signal, and a select signal. The second circuit may be configured to generate the select signal in response to the valid word signal, a start of frame signal, and end of frame signal and the data output signal. The select signal may adjust a starting point of each of the words to match a starting point of the first word.

摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于数据输入信号，有效字信号和选择信号而产生数据输出信号。 第二电路可以被配置为响应于有效字信号，帧信号的开始以及帧结束信号和数据输出信号而产生选择信号。 选择信号可以调整每个单词的起始点以匹配第一个单词的起始点。

公开(公告)号：US06891765B2

公开(公告)日：2005-05-10

申请号：US10634669

申请日：2003-08-05

申请人： Alon Saado

发明人： Alon Saado

IPC分类号： G06F9/445 ,  G06F11/00 ,  G06F12/06 ,  G11C7/00 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C17/10 ,  G11C29/00

CPC分类号： G06F8/66 ,  G06F9/30181 ,  G06F12/0638 ,  G11C17/10

摘要： The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.