公开(公告)号：US07829883B2

公开(公告)日：2010-11-09

申请号：US10777576

申请日：2004-02-12

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 碳纳米管场效应晶体管，碳纳米管场效应晶体管阵列，器件结构和器件结构阵列。 叠层器件结构包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘。 栅电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 栅电极具有被栅极电介质覆盖的侧壁和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20100273298A1

公开(公告)日：2010-10-28

申请号：US12830510

申请日：2010-07-06

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/98

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of elongated parallel catalyst strips on a horizontal surface, and growing carbon nanotubes from the catalyst in the presence of a directional flow of reactant gases.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，定向碳纳米管通过在水平表面上形成一系列细长的平行催化剂条而形成，并且在有反应气体的定向流的存在下从催化剂生长碳纳米管。

公开(公告)号：US07750406B2

公开(公告)日：2010-07-06

申请号：US11877871

申请日：2007-10-24

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  John Gerard Gaudiello ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L23/62 ,  H01L29/94

CPC分类号： H01L21/76264

摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

摘要翻译： 设计结构体现在机器可读介质中，用于设计，制造或测试设计，其中设计结构包括以混合衬底形成的器件，其特征在于具有不同晶体取向的半导体岛。 绝缘层将至少一个不同晶体取向的岛分成相互排列的器件和体区。 身体区域可以相对于装置区域电浮动。

公开(公告)号：US07727848B2

公开(公告)日：2010-06-01

申请号：US12169806

申请日：2008-07-09

申请人： Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L21/331

CPC分类号： H01L27/0921 ,  H01L21/823878 ,  H01L29/78

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。 在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。 沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。 可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

公开(公告)号：US07579272B2

公开(公告)日：2009-08-25

申请号：US11670778

申请日：2007-02-02

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： H01L21/4763

CPC分类号： H01L21/02115 ,  B82Y10/00 ,  H01L21/02282 ,  H01L21/3146 ,  H01L21/3185 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76888 ,  H01L2221/1047

摘要： Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

摘要翻译： 形成用于制造半导体器件的低k电介质层并使用低k电介质材料制造半导体结构的方法。 低k介电材料包括碳纳米结构，如碳纳米管或碳​​棒球，其特征在于绝缘电子状态。 碳纳米结构可以在包含碳纳米结构的层在基底上形成之前或之后转变为绝缘电子状态。 将碳纳米结构转化为绝缘电子态的一种方法是氟化。

公开(公告)号：US07566613B2

公开(公告)日：2009-07-28

申请号：US11221118

申请日：2005-09-07

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell

IPC分类号： H01L21/8244

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US20090001481A1

公开(公告)日：2009-01-01

申请号：US11768270

申请日：2007-06-26

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Jack A. Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Jack A. Mandelman ,  William Robert Tonti

IPC分类号： H01L27/105 ,  H01L21/8238

CPC分类号： H01L27/0733 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L28/40

摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的浅沟槽隔离（STI）区域，以及（c）半导体衬底上的第一半导体晶体管。 第一半导体晶体管包括（I）第一源极/漏极区域，（ii）第二源极/漏极区域，以及（iii）第一栅极电极区域。 第一和第二源/漏区掺杂相同的掺杂极性。 半导体结构还包括在半导体衬底中的第一掺杂区域。 第一掺杂区域位于STI区域的第一侧壁和底壁上。 第一掺杂区域与第二源极/漏极区域直接物理接触。 第一掺杂区域和第二源极/漏极区域掺杂相同的掺杂极性。

公开(公告)号：US20080227264A1

公开(公告)日：2008-09-18

申请号：US11926661

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/76

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US07397692B1

公开(公告)日：2008-07-08

申请号：US11612809

申请日：2006-12-19

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack A. Mandelman

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack A. Mandelman

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.

摘要翻译： 一个SRAM单元。 SRAM单元包括第一CMOS反相器和第二CMOS反相器，连接到第二反相器的输出的第一反相器的输入和连接到第一反相器的输出的第二反相器的输入， 第一CMOS反相器的输出和第一电容器的第一板，第一电容器的第二板连接到电源的高电压端子; 插入在所述第二CMOS反相器的输出端和第二电容器的第一板之间的第二MOSFET，所述第二电容器的第二板连接到所述电源的高电压端子; 以及连接到第一MOSFET的栅极和第二MOSFET的栅极的控制信号线。

公开(公告)号：US07273794B2

公开(公告)日：2007-09-25

申请号：US10732953

申请日：2003-12-11

申请人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。