公开(公告)号：US5663925A

公开(公告)日：1997-09-02

申请号：US581472

申请日：1995-12-18

申请人： Huy Thanh Vo

发明人： Huy Thanh Vo

IPC分类号： G11C7/14 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/14 ,  G11C8/18

摘要： In a memory device such as a DRAM or multiport DRAM, each of a plurality of memory cells includes an access transistor with a gate connected to a word line and a storage capacitor with a storage node connected through the access transistor to a digit line. Data is transferred on the digit line to and from the storage capacitor when the word line is activated and the access transistor enabled thereby. According to the present invention, a timing control circuit is provided to control deactivation of the word line. The timing control circuit includes a digit-write/transfer model that simulates a read-write cycle in a DRAM or a serial write transfer operation in a multiport DRAM. The digit-write transfer model produces an output signal indicating the state of the modeled data transfer operation. The timing control circuit also includes a reference voltage circuit and a level comparator. The level comparator compares the model output signal to the reference voltage provided by the reference voltage circuit. The level comparator includes a sensitive analog multi-stage current mirror differential amplifier circuit and produces a signal input to a RAS timing chain circuit which deactivates the word line upon completion of the modeled data transfer operation.

摘要翻译： 在诸如DRAM或多端口DRAM的存储器件中，多个存储器单元中的每一个包括具有连接到字线的栅极的存取晶体管和具有通过存取晶体管连接到数字线的存储节点的存储电容器。 当字线被激活并且由此启用存取晶体管时，数据在存储电容器的数字线上被传送到存储电容器。 根据本发明，提供一种定时控制电路来控制字线的去激活。 定时控制电路包括模拟DRAM中的读写周期或多端口DRAM中的串行写传输操作的数字写/传输模型。 数位写传输模型产生一个指示建模数据传输操作状态的输出信号。 定时控制电路还包括参考电压电路和电平比较器。 电平比较器将模型输出信号与参考电压电路提供的参考电压进行比较。 电平比较器包括灵敏的模拟多级电流镜差分放大器电路，并且产生对RAS定时链电路的信号输入，其在建模的数据传送操作完成时停用字线。