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    Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices
    21.
    发明授权
    Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices 有权
    在设备之间具有点到点（PTP）和点到两点（PTTP）链路的存储器系统

    公开(公告)号：US07778042B2

    公开(公告)日：2010-08-17

    申请号：US12143126

    申请日：2008-06-20

    申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    IPC分类号： H05K1/11

    CPC分类号： G11C5/063

    摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

    摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

    Multi-functional cyclic siloxane compound and process for preparing dielectric film by using siloxane-based polymer prepared from the compound
    22.
    发明授权
    Multi-functional cyclic siloxane compound and process for preparing dielectric film by using siloxane-based polymer prepared from the compound 有权
    多功能环状硅氧烷化合物以及使用由该化合物制备的硅氧烷类聚合物制备电介质膜的方法

    公开(公告)号：US07750176B2

    公开(公告)日：2010-07-06

    申请号：US12458009

    申请日：2009-06-29

    申请人： Hyeon Jin Shin ,  Hyun Dam Jeong ,  Jong Baek Seon ,  Sang Kook Mah ,  Jin Heong Yim ,  Jae Jun Lee ,  Kwang Hee Lee ,  Jung Bae Kim

    发明人： Hyeon Jin Shin ,  Hyun Dam Jeong ,  Jong Baek Seon ,  Sang Kook Mah ,  Jin Heong Yim ,  Jae Jun Lee ,  Kwang Hee Lee ,  Jung Bae Kim

    IPC分类号： C07F7/08 ,  C08G77/04 ,  B32B9/04

    CPC分类号： C07F7/21 ,  Y10T428/31663

    摘要： A multi-functional cyclic siloxane compound (A), a siloxane-based (co)polymer prepared from the compound (A), or compound (A) and at least one of a Si monomer having organic bridges (B), an acyclic alkoxy silane monomer (C), and a linear siloxane monomer (D); and a process for preparing a dielectric film using the polymer. The siloxane compound of the present invention is highly reactive, so the polymer prepared from the compound is excellent in mechanical properties, thermal stability and crack resistance, and has a low dielectric constant resulting from compatibility with conventional pore-generating materials. Furthermore, a low content of carbon and high content of SiO2 enhance its applicability to the process of producing a semiconductor, wherein it finds great use as a dielectric film.

    摘要翻译： 多官能环状硅氧烷化合物（A），由化合物（A）或化合物（A）制备的硅氧烷类（共）聚合物和至少一种具有有机桥（B）的Si单体，无环烷氧基 硅烷单体（C）和直链硅氧烷单体（D）; 以及使用该聚合物制备电介质膜的方法。 本发明的硅氧烷化合物具有高反应性，因此由该化合物制备的聚合物的机械性能，热稳定性和抗裂性优异，并且由于与常规孔产生材料的相容性而具有低的介电常数。 此外，低含量的碳和高含量的SiO 2增强了其在制造半导体的过程中的适用性，其中它被广泛用作电介质膜。

    METHOD AND APPARATUS FOR PROVIDING AND RECEIVING THREE-DIMENSIONAL DIGITAL CONTENTS
    24.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING AND RECEIVING THREE-DIMENSIONAL DIGITAL CONTENTS 有权
    提供和接收三维数字内容的方法和装置

    公开(公告)号：US20090257452A1

    公开(公告)日：2009-10-15

    申请号：US12274864

    申请日：2008-11-20

    申请人： Jae-jun LEE ,  Yong-seok JANG ,  Seong-sin JOO ,  Jae-seung KIM

    发明人： Jae-jun LEE ,  Yong-seok JANG ,  Seong-sin JOO ,  Jae-seung KIM

    IPC分类号： H04L12/56 ,  H04J3/00

    CPC分类号： H04N13/161 ,  H04L65/607

    摘要： Provided are a method and an apparatus for providing three-dimensional (3D) digital content by using a conventional system for providing two-dimensional (2D) digital content. The method includes generating an elementary stream (ES) regarding first data of 2D digital content, generating an ES regarding second data of 3D digital content, packetizing the ESs of the first data and the second data, and recording) the packetized second data and content information of the second data within header information of multiplexed stream of the packetized first data.

    摘要翻译： 提供了一种通过使用用于提供二维（2D）数字内容的常规系统来提供三维（3D）数字内容的方法和装置。 该方法包括生成关于2D数字内容的第一数据的基本流（ES），产生关于3D数字内容的第二数据的ES，打包第一数据和第二数据的ES并且记录）分组化的第二数据和内容 分组化的第一数据的复用流的报头信息内的第二数据的信息。

    Composition for producing organic insulator comprising an organic-inorganic metal hybrid material
    25.
    发明申请
    Composition for producing organic insulator comprising an organic-inorganic metal hybrid material 失效
    用于制造包含有机 - 无机金属混合材料的有机绝缘体的组合物

    公开(公告)号：US20090230388A1

    公开(公告)日：2009-09-17

    申请号：US12379146

    申请日：2009-02-13

    申请人： Jung Han Shin ,  Jae Jun Lee ,  Chang Ju Kim ,  Sang Yoon Lee

    发明人： Jung Han Shin ,  Jae Jun Lee ,  Chang Ju Kim ,  Sang Yoon Lee

    IPC分类号： H01L51/10 ,  B05D5/12 ,  C08L83/08

    CPC分类号： C08G77/58 ,  C08L83/14 ,  H01L51/052 ,  H01L51/0525 ,  C08L2666/02

    摘要： A composition for producing an organic insulator is provided which comprises an organic-inorganic hybrid material (as defined). The hybrid material shows high solubility in organic solvents and monomers, and superior adhesion to substrates. In addition, the hybrid material displays a high dielectric constant and a high degree of crosslinking. Based on these advantages, the composition comprising the organic-inorganic hybrid material can be utilized during the fabrication of various electronic devices by a wet process. A method for producing the organic insulator while utilizing the composition also is provided, as well as the resulting organic insulator, and an organic thin film transistor which incorporates the resulting insulating layer.

    摘要翻译： 提供了一种用于生产有机绝缘体的组合物，其包含有机 - 无机混合材料（如所定义的）。 杂化材料在有机溶剂和单体中表现出高溶解度，并且对基材具有优异的粘附性。 此外，混合材料显示高介电常数和高交联度。 基于这些优点，可以在通过湿法制造各种电子器件期间利用包含有机 - 无机混合材料的组合物。 还提供了一种在使用组合物的同时制造有机绝缘体的方法，以及所得的有机绝缘体和结合了所得绝缘层的有机薄膜晶体管。

    Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device
    27.
    发明授权
    Delay locked loop circuit for a synchronous semiconductor memory device and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device 有权
    用于同步半导体存储器件的延迟锁定环路电路和产生关于连接到同步半导体存储器件的数据引脚的负载的信息的方法

    公开(公告)号：US07474572B2

    公开(公告)日：2009-01-06

    申请号：US12123539

    申请日：2008-05-20

    申请人： Jae-Jun Lee ,  Hoe-Ju Chung

    发明人： Jae-Jun Lee ,  Hoe-Ju Chung

    IPC分类号： G11C7/00

    CPC分类号： H03L7/0812

    摘要： A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

    摘要翻译： 用于同步半导体存储器件的延迟锁定环（DLL）电路，其可以根据外部负载的大小来控制DLL电路内的反馈回路的延迟时间，以及生成关于连接到数据的负载的信息的方法 提供同步半导体存储器件的引脚。 DLL电路包括复制输出驱动器，延迟第一延迟时间的内部时钟信号以输出第一内部时钟信号，第一延迟时间是当输出驱动器第一次加载时产生的内部时钟信号的延迟时间 第一幅度的第一延迟连接到输出驱动器的输出端，以及传输/延迟电路，当第一负载连接到输出端时，将第一延迟内部时钟信号传送到相位检测器作为第二延迟内部时钟信号， 并且通过将所述第一延迟内部时钟信号延迟第二延迟时间，将所述第二延迟内部时钟信号输出到相位检测器，所述第二延迟时间是由所述输出驱动器产生的内部时钟信号的延迟时间， 大于第一幅度的第二幅度连接到输出端。

    MEMORY SYSTEM HAVING POINT-TO-POINT (PTP) AND POINT-TO-TWO-POINT (PTTP) LINKS BETWEEN DEVICES
    28.
    发明申请
    MEMORY SYSTEM HAVING POINT-TO-POINT (PTP) AND POINT-TO-TWO-POINT (PTTP) LINKS BETWEEN DEVICES 有权
    具有点到点（PTP）和点到两点（PTTP）之间的连接的存储器系统

    公开(公告)号：US20080247212A1

    公开(公告)日：2008-10-09

    申请号：US12143126

    申请日：2008-06-20

    申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063

    摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

    摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

    METHOD FOR PROVIDING MOBILE SERVICE USING CODE-PATTERN
    29.
    发明申请
    METHOD FOR PROVIDING MOBILE SERVICE USING CODE-PATTERN 失效
    使用代码模式提供移动服务的方法

    公开(公告)号：US20080245870A1

    公开(公告)日：2008-10-09

    申请号：US12140960

    申请日：2008-06-17

    申请人： Jae-Jun Lee ,  Young-Jun Shin

    发明人： Jae-Jun Lee ,  Young-Jun Shin

    IPC分类号： G06F17/00

    CPC分类号： G06F17/30879 ,  G06K7/10722 ,  G06K19/06037 ,  G06Q20/14 ,  G06Q20/32 ,  G06Q20/322 ,  G06Q20/3276 ,  H04L29/06 ,  H04L29/12594 ,  H04L61/30 ,  H04L67/04 ,  H04L69/329 ,  H04M1/2755 ,  H04M1/72561 ,  H04M3/42 ,  H04M3/493 ,  H04M15/68 ,  H04M2215/0196 ,  H04N1/00244 ,  H04N1/00307 ,  H04N1/00326 ,  H04N1/00334 ,  H04N2201/0084 ,  H04W4/16 ,  Y10S379/91

    摘要： A method and apparatus for providing a mobile service with the use of a code pattern is disclosed In one embodiment, the method comprising: taking a photograph of a code pattern image, decoding the photographed code pattern image so as to obtain code information, extracting uniform resourse locator (URL) information corresponding to the code information, transmitting a content information request message to a service provider server corresponding to the URL information, and receiving content information corresponding to the URL information from the service provider server. According to embodiments of the present invention, it is possible to provide various and convenient mobile services to mobile terminal users using a mobile terminal, having a camera, and a code pattern containing the URL information.

    摘要翻译： 公开了一种使用代码图案提供移动业务的方法和装置。在一个实施例中，该方法包括：拍摄代码图像图像，解码所拍摄的代码图形图像，以获得代码信息，提取均匀 对应于代码信息的资源定位符（URL）信息，向与URL信息相对应的服务提供者服务器发送内容信息请求消息，以及从服务提供商服务器接收与URL信息对应的内容信息。 根据本发明的实施例，可以使用具有相机的移动终端和包含URL信息的代码模式向移动终端用户提供各种和方便的移动服务。

    DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE
    30.
    发明申请
    DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE 有权
    用于同步半导体存储器件的延迟锁定环路电路和产生与连接到同步半导体存储器件的数据引脚的负载的信息的方法

    公开(公告)号：US20080219065A1

    公开(公告)日：2008-09-11

    申请号：US12123539

    申请日：2008-05-20

    申请人： JAE-JUN LEE ,  HOE-JU CHUNG

    发明人： JAE-JUN LEE ,  HOE-JU CHUNG

    IPC分类号： G11C7/00

    CPC分类号： H03L7/0812

    摘要： A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal.

    摘要翻译： 用于同步半导体存储器件的延迟锁定环（DLL）电路，其可以根据外部负载的大小来控制DLL电路内的反馈回路的延迟时间，以及生成关于连接到数据的负载的信息的方法 提供同步半导体存储器件的引脚。 DLL电路包括复制输出驱动器，延迟第一延迟时间的内部时钟信号以输出第一内部时钟信号，第一延迟时间是当输出驱动器第一次加载时产生的内部时钟信号的延迟时间 第一幅度的第一延迟连接到输出驱动器的输出端，以及传输/延迟电路，当第一负载连接到输出端时，将第一延迟内部时钟信号传送到相位检测器作为第二延迟内部时钟信号， 并且通过将所述第一延迟内部时钟信号延迟第二延迟时间，将所述第二延迟内部时钟信号输出到所述相位检测器，所述第二延迟时间是由所述输出驱动器产生的内部时钟信号的延迟时间， 大于第一幅度的第二幅度连接到输出端。