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    Dual probe test structures for semiconductor integrated circuits
    22.
    发明授权
    Dual probe test structures for semiconductor integrated circuits 有权
    半导体集成电路的双探针测试结构

    公开(公告)号：US06636064B1

    公开(公告)日：2003-10-21

    申请号：US09648092

    申请日：2000-08-25

    申请人： Akella V. S. Satya ,  David L. Adler ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker

    发明人： Akella V. S. Satya ,  David L. Adler ,  Neil Richardson ,  Kurt H. Weiner ,  David J. Walker

    IPC分类号： G01R3128

    CPC分类号： H01L22/34 ,  G01N21/66 ,  G01N21/9501 ,  G01N21/956 ,  G01R31/2884 ,  G01R31/307 ,  H01J2237/2817

    摘要： Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.

    摘要翻译： 公开了具有上层和下层的半导体管芯。 模具包括形成在半导体管芯的下金属层中的下部测试结构。 下导电测试结构具有第一端和第二端，其中第一端耦合到预定的电压电平。 模具还具有形成在下金属层上的绝缘层和形成在半导体管芯的上金属层中的上测试结构。 上导电测试结构与下导电测试结构的第二端耦合，并且上金属层形成在绝缘层上。 芯片还包括与上测试结构耦合的至少一个探针焊盘。 优选地，下测试结构的第一端耦合到标称接地电位。 在另一实施方案中，上测试结构是电压对比元件。 在另一实施例中，公开了具有扫描区域的半导体管芯。 半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。 模具包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分地位于扫描区域内。 第一多个测试结构或第二多个测试结构具有耦合到至少一个测试结构的探针焊盘。

    ABSORBER REPAIR IN SUBSTRATE FABRICATED PHOTOVOLTAICS
    23.
    发明申请
    ABSORBER REPAIR IN SUBSTRATE FABRICATED PHOTOVOLTAICS 审中-公开
    吸收体修复基底织物光伏

    公开(公告)号：US20110312120A1

    公开(公告)日：2011-12-22

    申请号：US13151113

    申请日：2011-06-01

    申请人： Kurt H. Weiner ,  Gaurav Verma

    发明人： Kurt H. Weiner ,  Gaurav Verma

    IPC分类号： H01L31/18

    CPC分类号： H01L31/186 ,  H01L31/03923 ,  H01L31/03925 ,  Y02E10/541 ,  Y02P70/521

    摘要： The invention relates generally to methods of repairing defects in thin films. Void defects in thin films are repaired using methods that take advantage of substrate manufacturing protocols rather than conventional superstrate manufacturing protocols. Methods described herein are simple, robust and compatible with existing processes and equipment used in the manufacture of superstrate devices.

    摘要翻译： 本发明一般涉及修复薄膜缺陷的方法。 使用利用衬底制造协议而不是常规上层制造协议的方法修复薄膜中的空隙缺陷。 本文描述的方法是简单的，稳健的并且与用于制造覆盖装置的现有工艺和设备兼容。

    APPARATUS AND METHODS FOR FAST CHEMICAL ELECTRODEPOSITION FOR FABRICATION OF SOLAR CELLS
    25.
    发明申请
    APPARATUS AND METHODS FOR FAST CHEMICAL ELECTRODEPOSITION FOR FABRICATION OF SOLAR CELLS 有权
    用于制造太阳能电池的快速化学电沉积的装置和方法

    公开(公告)号：US20110290641A1

    公开(公告)日：2011-12-01

    申请号：US13081389

    申请日：2011-04-06

    申请人： Kurt H. Weiner ,  Gaurav Verma

    发明人： Kurt H. Weiner ,  Gaurav Verma

    IPC分类号： C25D19/00

    CPC分类号： H01L31/18 ,  C25D5/022 ,  C25D5/54 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  C25D21/12 ,  H01L31/022425 ,  Y02E10/50

    摘要： The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.

    摘要翻译： 本发明一般涉及电沉积装置和方法。 当通过电沉积沉积膜时，其中衬底具有固有电阻率，例如薄膜中的薄层电阻，本发明的方法和装置用于通过在衬底表面上形成多个欧姆接触将材料电沉积到衬底上， 从而克服固有的电阻和电沉积均匀的膜。 本发明的方法和装置在太阳能电池制造中特别有用。

    Methodologies for efficient inspection of test structures using electron beam scanning and step and repeat systems
    30.
    发明授权
    Methodologies for efficient inspection of test structures using electron beam scanning and step and repeat systems 有权
    使用电子束扫描和步骤和重复系统有效检查测试结构的方法

    公开(公告)号：US07198963B2

    公开(公告)日：2007-04-03

    申请号：US10638027

    申请日：2003-08-08

    申请人： Gaurav Verma ,  Kurt H. Weiner

    发明人： Gaurav Verma ,  Kurt H. Weiner

    IPC分类号： H01L21/66

    CPC分类号： H01L22/34 ,  G01R31/307

    摘要： Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure. Far each localized defect, the same charged particle beam based tool may then be used to generate a high resolution image of the localized defect whereby the high resolution image can later be used to classify the each defect. In one embodiment, the defect's presence and location are determined without rotating the test structure relative to the charged particle beam.

    摘要翻译： 公开了用于有效地检查电压对比度测试中的缺陷的技术。 在一个实施例中，方法和测试结构允许检查完全发生在带电粒子系统内。 在具体实施例中，公开了一种适用于电压对比度检查的半导体测试结构中的定位和成像缺陷的方法。 使用带电粒子束的工具来确定电压对比度测试结构内是否存在任何缺陷。 然后使用相同的带电粒子束工具来定位确定存在于电压对比度测试结构内的缺陷。 对于每个局部缺陷，可以使用相同的基于带电粒子束的工具来产生局部缺陷的高分辨率图像，由此可以使用高分辨率图像来分类每个缺陷。 在一个实施例中，在不使测试结构相对于带电粒子束旋转的情况下确定缺陷的存在和位置。