公开(公告)号：US08400828B2

公开(公告)日：2013-03-19

申请号：US13435901

申请日：2012-03-30

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

公开(公告)号：US20120195121A1

公开(公告)日：2012-08-02

申请号：US13435901

申请日：2012-03-30

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

摘要翻译： 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US07683452B2

公开(公告)日：2010-03-23

申请号：US11089366

申请日：2005-03-25

申请人： Narumi Ohkawa ,  Masayoshi Asano ,  Toshio Nomura

发明人： Narumi Ohkawa ,  Masayoshi Asano ,  Toshio Nomura

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14689

摘要： An image sensor has a plurality of pixels each with a photoelectric conversion element and a detection transistor the threshold voltage of which fluctuates in accordance with electrical charge generated in the photoelectric conversion element. The image sensor includes a second conductivity type shield region and a first conductivity type photoelectric conversion region; a first conductivity type well region linked to the photoelectric conversion region; a ring-like gate electrode; a second conductivity type source region at the inside of the ring-like gate electrode; a second conductivity type drain region. The image sensor further includes a potential pocket region that is formed in the well region below the ring-like gate electrode and accumulates the electrical charge, wherein the width of the gate electrode is formed narrower in the part adjacent to the photoelectric conversion region than in other parts.

摘要翻译： 图像传感器具有多个像素，每个像素具有光电转换元件和阈值电压根据光电转换元件中产生的电荷而波动的检测晶体管。 图像传感器包括第二导电类型屏蔽区域和第一导电类型光电转换区域; 连接到光电转换区的第一导电类型阱区; 环状栅电极; 位于环状栅电极内部的第二导电型源区; 第二导电类型漏极区域。 图像传感器还包括形成在环状栅极电极下方的阱区中的电势袋区域，并蓄积电荷，其中栅电极的宽度在与光电转换区相邻的部分形成得比在 其他部分。

公开(公告)号：US20060084208A1

公开(公告)日：2006-04-20

申请号：US11242648

申请日：2005-10-04

申请人： Masayoshi Asano ,  Toshio Nomura ,  Taiji Ema

发明人： Masayoshi Asano ,  Toshio Nomura ,  Taiji Ema

IPC分类号： H01L21/337

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823857

摘要： A simplified method of manufacturing a multi-voltage semiconductor integrated circuit device. A method of manufacturing a semiconductor device includes the steps of: forming a first gate insulating film with a first thickness in a first area of a semiconductor substrate: forming a second gate insulating film with a second thickness thinner than the first thickness in a second area of the semiconductor substrate; forming on gate electrodes on the first and second gate insulating films and leaving the first and second gate insulating films in the first and second areas; implanting impurity ions into the first and second areas via the first and second gate insulating films to dope impurities into the first area at a first low impurity concentration and into the second area at a second impurity concentration higher than the first impurity concentration; removing the first and second gate insulating films at least in an area where contacts are formed; and doping impurities at a high impurity concentration in an area including the area where contacts are formed, in the first and second areas.

摘要翻译： 一种制造多电压半导体集成电路器件的简化方法。 一种制造半导体器件的方法包括以下步骤：在半导体衬底的第一区域中形成具有第一厚度的第一栅极绝缘膜：在第二区域中形成具有比第一厚度更薄的第二厚度的第二栅极绝缘膜 的半导体衬底; 在所述第一和第二栅极绝缘膜上的栅电极上形成并且在所述第一和第二区域中留下所述第一和第二栅极绝缘膜; 通过第一和第二栅极绝缘膜将杂质离子注入到第一和第二区域中，以在第一低杂质浓度下杂质掺杂到第一区域，并以高于第一杂质浓度的第二杂质浓度进入第二区域; 至少在形成接触的区域中去除第一和第二栅极绝缘膜; 并且在第一和第二区域中在包括形成接触的区域的区域中掺杂高杂质浓度的杂质。

公开(公告)号：US06326254B1

公开(公告)日：2001-12-04

申请号：US09070786

申请日：1998-05-01

申请人： Taiji Ema ,  Satoru Miyoshi ,  Tatsumi Tsutsui ,  Masaya Katayama ,  Masayoshi Asano ,  Kenichi Kanazawa

发明人： Taiji Ema ,  Satoru Miyoshi ,  Tatsumi Tsutsui ,  Masaya Katayama ,  Masayoshi Asano ,  Kenichi Kanazawa

IPC分类号： H01L218238

CPC分类号： H01L27/0928

摘要： Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

摘要翻译： n型和p型阱形成在p型衬底中。 p型阱也形成在n型阱中。 同时通过相同的工艺形成p型阱，以使MOS晶体管具有不同的阈值电压。 在n阱的p阱中形成具有长栅极长度和低阈值电压的MOS晶体管，并且在栅极外部的p阱中形成具有短栅极长度和高阈值电压的MOS晶体管 n-well 保险丝以高密度形成在n型阱中的p型阱上。