公开(公告)号：US20130140579A1

公开(公告)日：2013-06-06

申请号：US13310074

申请日：2011-12-02

申请人： Hasan Sharifi ,  Alexandros D. Margomenos ,  Ara K. Kurdoghlian ,  Miroslav Micovic ,  Keisuke Shinohara ,  Colleen M. Butler

发明人： Hasan Sharifi ,  Alexandros D. Margomenos ,  Ara K. Kurdoghlian ,  Miroslav Micovic ,  Keisuke Shinohara ,  Colleen M. Butler

IPC分类号： H01L29/20 ,  H01L23/52 ,  H01L21/768

CPC分类号： H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.

摘要翻译： 将苯并环丁烯（BCB）层与基板一体化的方法与相应的装置一起提供。 一种方法包括在衬底上形成第一BCB层，并在第一BCB层上以及在由第一金属层限定的通孔内沉积第一金属层。 该方法还在第一金属层上形成第二BCB层，并在第二BCB层上以及由第二金属层限定的通孔内沉积第二金属层。 第二金属层延伸穿过由第二金属层限定的通孔，以建立与第一金属层的可操作连接。 第一和第二金属层独立于与由衬底承载的任何电路元件的电连接，但第一和第二金属层将第二BCB层固定到下面的结构并降低分层的可能性。

公开(公告)号：US07098490B2

公开(公告)日：2006-08-29

申请号：US10832691

申请日：2004-04-26

申请人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Peter W. Deelman

发明人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Peter W. Deelman

IPC分类号： H01L29/772

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/7787

摘要： The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising AlxGa1−xN. The Al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the Al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.

摘要翻译： 本发明提供了一种GaN基DHFET，其帮助将2DEG限制到沟道层，并且减少2DHG。 本发明提供了具有包含GaN的沟道层和包括Al x Ga 1-x N的缓冲层的GaN DHFET。 缓冲层中的Al含量是使用图表基于沟道层的厚度特别选择的。 通过根据本发明提供的图来选择缓冲层中的Al含量和沟道层的厚度，缓冲层有助于将2DEG限制到沟道层的能力得到改善。

公开(公告)号：US07025501B2

公开(公告)日：2006-04-11

申请号：US10870828

申请日：2004-06-17

申请人： Blaine D. Johs ,  Miroslav Micovic

发明人： Blaine D. Johs ,  Miroslav Micovic

IPC分类号： G01K11/32 ,  G01J5/08 ,  G01J4/04

CPC分类号： G01K11/125

摘要： A method for tracking change in Temperature of Uniaxial or Biaxial Anisotropic Samples utilizing polarized electromagnetic radiation.

摘要翻译： 利用极化电磁辐射跟踪单轴或双轴各向异性样品的温度变化的方法。

公开(公告)号：US06884704B2

公开(公告)日：2005-04-26

申请号：US10634348

申请日：2003-08-04

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

IPC分类号： H01L21/24 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L29/20 ,  H01L29/45 ,  H01L21/48 ,  H01L21/38

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

摘要翻译： 说明了在随后的高温处理步骤中制造保护欧姆金属触点和器件通道的半导体器件的方法。 封装层用于覆盖通道和欧姆金属触点。 本发明提供一种其上沉积有多个半导体层的衬底。 半导体层用作器件的通道。 半导体层被封装层覆盖。 去除封装层和多个半导体层的一部分，其中沉积欧姆金属接触。 然后将欧姆金属触点退火以帮助降低其电阻。 封装层确保在退火步骤期间欧姆金属触点不迁移，并且该通道不会受退火步骤期间所需的高温的损害。

公开(公告)号：US06670653B1

公开(公告)日：2003-12-30

申请号：US09364730

申请日：1999-07-30

申请人： Miroslav Micovic ,  Daniel P. Docter ,  Mehran Matloubian

发明人： Miroslav Micovic ,  Daniel P. Docter ,  Mehran Matloubian

IPC分类号： H01L21331

CPC分类号： H01L29/66318 ,  H01L29/155 ,  H01L29/7371

摘要： A Double Heterojunction Bipolar Transistor (DHBT) is disclosed employing a collector of InP, an emitter of InP or other material such as InAlAs, and a base of either a selected InxGa1−xAsySb1−y compound, which preferably is lattice-matched to InP or may be somewhat compressively strained thereto, or of a superlattice which mimics the selected InGaAsSb compound. When an emitter having a conduction band non-aligned with that of the base is used, such as InAlAs, the base-emitter junction is preferably graded using either continuous or stepped changes in bulk material, or using a chirped superlattice. Doping of the junction may include one or more delta doping layer to improve the shift of conduction band discontinuities provided by a grading layer, or to permit a wider depletion region.

摘要翻译： 公开了使用InP的集电极，InP的发射极或诸如InAlAs的其它材料的双异质结双极晶体管（DHBT），以及选择的In x Ga 1-x As y Sb 1-y化合物的碱，其优选与InP或 可能有些压缩应变，或模拟所选InGaAsSb化合物的超晶格。 当使用具有与碱的不对准的导带的发射体（例如InAlAs）时，基极 - 发射极结优选地使用块状材料的连续或阶梯变化或使用啁啾超晶格进行分级。 结的掺杂可以包括一个或多个δ掺杂层，以改善由分级层提供的导带不连续性的偏移，或者允许更宽的耗尽区。

公开(公告)号：US06287946B1

公开(公告)日：2001-09-11

申请号：US09305896

申请日：1999-05-05

申请人： Miroslav Micovic ,  Daniel P. Docter

发明人： Miroslav Micovic ,  Daniel P. Docter

IPC分类号： H01L2128

CPC分类号： B82Y15/00 ,  H01L21/28575 ,  H01L29/452

摘要： A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.

摘要翻译： 一种降低金属与InP半导体化合物之间的金属与半导体界面的比接触电阻率的方法。 该方法包括增加半导体化合物中的V族元素（P）的量的步骤，使半导体化合物的非化学计量比V族元素的过量浓度高于化学计量值的至少0.1％ 。

公开(公告)号：US09496197B1

公开(公告)日：2016-11-15

申请号：US14495755

申请日：2014-09-24

申请人： Miroslav Micovic ,  Alexandros D. Margomenos ,  Keisuke Shinohara ,  Andrea Corrion

发明人： Miroslav Micovic ,  Alexandros D. Margomenos ,  Keisuke Shinohara ,  Andrea Corrion

IPC分类号： H01L23/373 ,  H01L23/34 ,  H01L21/306 ,  H01L23/00 ,  H01L29/80

CPC分类号： H01L23/34 ,  H01L21/30617 ,  H01L21/30625 ,  H01L23/3677 ,  H01L23/3732 ,  H01L24/27 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66871 ,  H01L29/812 ,  H01L2924/01006 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/142

摘要： Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and a drain on the substrate, and a poly-diamond dielectric thermally coupled to the first gate wherein the poly-diamond dielectric facilitates heat removal from a top of the FET.

摘要翻译： 提供了用于从包括衬底，第一源，第一栅极和漏极在衬底上的场效应晶体管（FET）散热和扩散的装置和方法，以及热耦合到第一栅极的多金刚石电介质，其中 该多晶金刚石介质有利于从顶部排出热量。

公开(公告)号：US08558281B1

公开(公告)日：2013-10-15

申请号：US13310473

申请日：2011-12-02

申请人： Dean C. Regan ,  Keisuke Shinohara ,  Andrea Corrion ,  Ivan Milosavljevic ,  Miroslav Micovic ,  Peter J. Willadsen ,  Colleen M. Butler ,  Hector L. Bracamontes ,  Bruce T. Holden ,  David T. Chang

发明人： Dean C. Regan ,  Keisuke Shinohara ,  Andrea Corrion ,  Ivan Milosavljevic ,  Miroslav Micovic ,  Peter J. Willadsen ,  Colleen M. Butler ,  Hector L. Bracamontes ,  Bruce T. Holden ,  David T. Chang

IPC分类号： H01L29/205

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462

摘要： A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.

摘要翻译： 一种制造用于场效应晶体管的栅极结构的方法，该场效应晶体管在衬底上具有缓冲层，沟道层上的沟道层和势垒层包括形成包含硅的栅极，在任一侧和相邻的第一侧上形成第一材料的第一侧壁 到栅极，选择性地蚀刻到缓冲层中以形成用于场效应晶体管的台面，在所述台面上沉积材料层，在所述台面上平坦化所述材料层以形成平坦化表面，使得所述栅极的顶部， 第一侧壁和台面上的材料层的顶部在相同的平坦化表面上，在平面化表面上沉积金属，退火以将栅极形成金属硅化栅极，并蚀刻以除去多余的非硅化金属。

公开(公告)号：US08383471B1

公开(公告)日：2013-02-26

申请号：US13083916

申请日：2011-04-11

申请人： Keisuke Shinihara ,  Andrea Corrion ,  Miroslav Micovic ,  Paul B. Hashimoto ,  Shawn D. Burnham ,  Hooman Kazemi ,  Peter J. Willadsen ,  Dean C. Regan

发明人： Keisuke Shinihara ,  Andrea Corrion ,  Miroslav Micovic ,  Paul B. Hashimoto ,  Shawn D. Burnham ,  Hooman Kazemi ,  Peter J. Willadsen ,  Dean C. Regan

IPC分类号： H01L21/338

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783

摘要： A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.

摘要翻译： 制造GaN HEMT的方法包括在衬底上生长第一外延层，在第一外延层上生长第二外延层，在第二外延层上生长第三外延层，在第三外延层上沉积第一电介质膜， 使用介电膜形成第一侧壁电介质间隔件，形成邻近所述第一侧壁电介质间隔物的侧壁门。 侧壁浇口的长度可以小于50nm。

公开(公告)号：US08030688B2

公开(公告)日：2011-10-04

申请号：US12486686

申请日：2009-06-17

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

摘要翻译： 说明了在随后的高温处理步骤中制造保护欧姆金属触点和器件通道的半导体器件的方法。 封装层用于覆盖通道和欧姆金属触点。 本发明提供一种其上沉积有多个半导体层的衬底。 半导体层用作器件的通道。 半导体层被封装层覆盖。 去除封装层和多个半导体层的一部分，其中沉积欧姆金属接触。 然后将欧姆金属触点退火以帮助降低它们的电阻。 封装层确保在退火步骤期间欧姆金属接触不迁移，并且该通道不会受退火步骤期间所需的高温的损害。