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    Delay locked loops and methods that shift the phase of a delayed clock signal based on a reference phase value
    22.
    发明授权
    Delay locked loops and methods that shift the phase of a delayed clock signal based on a reference phase value 失效
    延迟锁定环路和基于参考相位值移位延迟时钟信号的相位的方法

    公开(公告)号：US06625242B1

    公开(公告)日：2003-09-23

    申请号：US09466395

    申请日：1999-12-17

    申请人： Chang-sik Yoo ,  Sang-bo Lee

    发明人： Chang-sik Yoo ,  Sang-bo Lee

    IPC分类号： H03D324

    CPC分类号： H03L7/0814

    摘要： A delay locked loop generates an advanced clock signal synchronized with a reference clock signal. The delay locked loop includes an input buffer, a variable delay circuit, a delay compensation circuit, a phase shifter, a delay controller, a phase sensing pump and a phase inversion controller. The variable delay circuit includes a multiplicity of delay terminals. The number of enabled delay terminals is controlled by a counting signal group. In the phase shifter, the phase of an output signal of the variable delay circuit generates the advanced clock signal with a phase of the reference clock signal. When the compared phase difference is more than Π, the phase shifter inverts a delayed clock signal to generate the advanced clock signal. When the compared phase difference is less than Π, the delayed clock signal is non-inverted to be generated as the advanced clock signal.

    摘要翻译： 延迟锁定环路产生与参考时钟信号同步的高级时钟信号。 延迟锁定环包括输入缓冲器，可变延迟电路，延迟补偿电路，移相器，延迟控制器，相位感测泵和相位转换控制器。 可变延迟电路包括多个延迟端子。 使能延迟端子的数量由计数信号组控制。 在移相器中，可变延迟电路的输出信号的相位以参考时钟信号的相位产生高级时钟信号。 当比较的相位差大于Pi时，移相器反转延迟的时钟信号以产生高级时钟信号。 当比较的相位差小于Pi时，延迟的时钟信号是不反相的，作为高级时钟信号产生。

    Integrated circuit memory devices having multiple data rate mode capability and methods of operating same
    23.
    发明授权
    Integrated circuit memory devices having multiple data rate mode capability and methods of operating same 失效
    具有多种数据速率模式能力的集成电路存储器件及其操作方法

    公开(公告)号：US06282128B1

    公开(公告)日：2001-08-28

    申请号：US09576987

    申请日：2000-05-23

    申请人： Sang-bo Lee

    发明人： Sang-bo Lee

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1012 ,  G11C7/1015 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C2207/107

    摘要： Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. Decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals. These circuits enable operation in both single and dual data rate modes and perform the functions of simultaneously transferring read data on the first and second global input/output lines to first and second data lines, respectively, during a first read time interval when a first column address signal is in a first logic state and simultaneously transferring read data on said first and second global input/output lines to the second and first data lines, respectively, during a second read time interval when the first column address signal is in a second logic state opposite the first logic state.

    摘要翻译： 可以以单数据速率模式和双数据速率模式（取决于模式选择信号的值）可操作的集成电路存储器件包括第一和第二存储单元阵列以及第一和第二全局输入/输出信号线（GIOF，GIOS） 耦合到第一和第二存储单元阵列。 提供了解码器和数据传输电路，并且这些电路响应于模式选择信号和列地址信号。 这些电路使得能够在单数据速率模式和双数据速率模式下操作，并且执行在第一读取时间间隔期间在第一读取时间间隔期间分别将第一和第二全局输入/输出线上的读取数据传送到第一和第二数据线的功能， 地址信号处于第一逻辑状态，并且当第一列地址信号处于第二逻辑时，分别在第二读取时间间隔期间将所述第一和第二全局输入/输出线上的读取数据传送到第二和第一数据线 状态与第一个逻辑状态相反。

    High-speed data input circuit for a synchronous memory device
    24.
    发明授权
    High-speed data input circuit for a synchronous memory device 失效
    用于同步存储器件的高速数据输入电路

    公开(公告)号：US5920511A

    公开(公告)日：1999-07-06

    申请号：US996192

    申请日：1997-12-22

    申请人： Sang-bo Lee ,  Jung-bae Lee

    发明人： Sang-bo Lee ,  Jung-bae Lee

    IPC分类号： G11C7/10 ,  G11C16/04

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/1078

    摘要： A data input circuit for a semiconductor memory device uses an echo clock generator to reduce the clock cycle time. The echo clock is transmitted in the memory device with the data, thereby reducing the effects of clock skew and increasing the overall device operation speed. The circuit is particularly applicable to double data rate synchronous DRAM (DDR-SDRAM) circuitry.

    摘要翻译： 用于半导体存储器件的数据输入电路使用回波时钟发生器来减少时钟周期时间。 回波时钟在数据存储器中传输，从而减少时钟偏移的影响，并提高整体设备的运行速度。 该电路特别适用于双倍数据速率同步DRAM（DDR-SDRAM）电路。

    Bit line sensing circuit and method of a semiconductor memory device
    25.
    发明授权
    Bit line sensing circuit and method of a semiconductor memory device 失效
    半导体存储器件的位线检测电路和方法

    公开(公告)号：US5638333A

    公开(公告)日：1997-06-10

    申请号：US487324

    申请日：1995-06-07

    申请人： Sang-Bo Lee

    发明人： Sang-Bo Lee

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/065

    摘要： A bit line sensing circuit of a semiconductor memory device having NMOS and PMOS sense amps connected to a bit line includes a variable delay path for variably controlling an interval of the operating time between the NMOS and PMOS sense amps in response to a power voltage sensing signal generated by sensing a power voltage level.

    摘要翻译： 具有连接到位线的NMOS和PMOS检测放大器的半导体存储器件的位线检测电路包括可变延迟路径，用于响应于电源电压感测信号可变地控制NMOS和PMOS检测放大器之间的工作时间的间隔 通过感测电源电压电平产生。

    SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL SENSE AMPLIFIER WITH ON/OFF CONTROL
    30.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL SENSE AMPLIFIER WITH ON/OFF CONTROL 审中-公开
    具有开/关控制的本地信号放大器的半导体存储器件

    公开(公告)号：US20110069568A1

    公开(公告)日：2011-03-24

    申请号：US12952328

    申请日：2010-11-23

    申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    IPC分类号： G11C7/08 ,  G11C7/12 ,  G11C7/22

    CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

    摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

    摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。