公开(公告)号：US20070037336A1

公开(公告)日：2007-02-15

申请号：US11425065

申请日：2006-06-19

Applicant: Hyung-Shin KWON ,  Seug-Gyu KIM

Inventor： Hyung-Shin KWON ,  Seug-Gyu KIM

IPC: H01L21/8234

CPC classification number: H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.

Abstract translation: 半导体器件在单元区域中具有正常的非凹入的间隔结构，并且在周边区域中形成有凹入的间隔结构。 凹陷的间隔结构通过蚀刻掩蔽细胞区域中的那些并且暴露在外围区域中的那些，然后进行蚀刻工艺而形成。 单元区域间隔物的增加的高度适于进一步防止在栅极互连形成期间的过度蚀刻，否则将导致通过间隔物蚀刻到衬底和随后的短路。 因此，也可以防止由于用于随后的互连接触的阻挡金属层意外地连接到下面的基板而发生的由于过蚀刻而引起的桥接缺陷。 此外，由于在周边区域设置凹陷的间隔结构，因此可以显着提高出现在100nm以下的栅极线宽度的硅化钴层的电阻分布。

公开(公告)号：US20060079060A1

公开(公告)日：2006-04-13

申请号：US11282156

申请日：2005-11-18

Applicant: Hyung-Shin Kwon

Inventor： Hyung-Shin Kwon

IPC: H01L21/336

CPC classification number: H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.

公开(公告)号：US07002223B2

公开(公告)日：2006-02-21

申请号：US10206809

申请日：2002-07-26

Applicant: Hyung-Shin Kwon

Inventor： Hyung-Shin Kwon

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0266 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.

Abstract translation: 本发明提供一种具有升高的源极/漏极的半导体器件及其制造方法。 在半导体器件中，在半导体衬底的预定区域限定有源区，并且形成栅电极以跨越有源区。 第一绝缘层图案和第二绝缘层图案依次层叠在栅电极的侧壁上，并且在有源区上形成与第一绝缘层图案和第二绝缘层图案的边缘相邻的硅外延层。 第一绝缘层图案的边缘从第二绝缘层图案的边缘突出以被预定区域被硅化的硅外延层覆盖。 此外，该方法包括限定有源区域，形成跨越有源区域的栅电极的半导体衬底，顺序地将第一和第二绝缘层图案堆叠在与栅电极的相对侧相邻的有源区域上，在该栅极电极上形成硅外延层 有源区域与第一和第二绝缘层图案的边缘相邻，并且硅化硅外延层的至少一部分。 与有源区接触的第一绝缘层图案的边缘从第二绝缘层图案的边缘突出，并且硅外延层覆盖第一绝缘层图案的突出边缘。

公开(公告)号：US20050029664A1

公开(公告)日：2005-02-10

申请号：US10932416

申请日：2004-09-02

Applicant: Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

Inventor： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

IPC: G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

Abstract: An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

Abstract translation: 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区， 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

公开(公告)号：US06767814B2

公开(公告)日：2004-07-27

申请号：US10100929

申请日：2002-03-18

Applicant: Hyung-Shin Kwon ,  Joon-Yong Joo ,  Kwang-Ok Koh ,  Sung-Bong Kim

Inventor： Hyung-Shin Kwon ,  Joon-Yong Joo ,  Kwang-Ok Koh ,  Sung-Bong Kim

IPC: H01L213205

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

公开(公告)号：US06552423B2

公开(公告)日：2003-04-22

申请号：US09785810

申请日：2001-02-15

Applicant: Young-Jae Song ,  Young-Shin Kwon ,  Kun-Dae Youm ,  Young-Soo Kim

Inventor： Young-Jae Song ,  Young-Shin Kwon ,  Kun-Dae Youm ,  Young-Soo Kim

IPC: H01L2348

CPC classification number: H01L23/055 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A high-density memory card comprises a base card and two packages fixedly mounted within the base card. The two packages are attached to the base card and face each other. In one embodiment, a first package comprises a first substrate and at least one memory chip, and a second package comprises a second substrate and at least one memory chip. A first surface of the first substrate has external connection pads formed thereon and is exposed from the memory card. A second surface of the first substrate has first connection pads formed thereon. The memory chips are mounted on the second surface and electrically connected to each other. A third surface of the second substrate is exposed from the memory card, and a fourth surface of the second substrate has second connection pads formed thereon. The memory chips are mounted on the fourth surface and electrically connected to each other. The base card further includes internal connection means, and the first and the second connection pads are electrically connected to the internal connection means. The external connection pads provide electrical connection between said internal connection means to an external system. By connecting two packages to the base card, the memory card of the present invention can increase the memory density of the smart cart four times or more. Also, the problems encountered in the conventional smart card manufacturing process or the test process due to the use of plural memory chips can be prevented.

Abstract translation: 高密度存储卡包括基卡和固定地安装在基卡内的两个封装。 两个包装被连接到基卡并面对彼此。 在一个实施例中，第一封装包括第一衬底和至少一个存储器芯片，第二封装包括第二衬底和至少一个存储器芯片。 第一基板的第一表面具有形成在其上的外部连接焊盘，并从存储卡露出。 第一基板的第二表面具有形成在其上的第一连接焊盘。 存储芯片安装在第二表面上并彼此电连接。 第二基板的第三表面从存储卡露出，第二基板的第四表面具有形成在其上的第二连接焊盘。 存储芯片安装在第四表面上并彼此电连接。 基座卡还包括内部连接装置，并且第一和第二连接垫电连接到内部连接装置。 外部连接焊盘提供所述内部连接装置与外部系统之间的电连接。 通过将两个包连接到基卡，本发明的存储卡可以将智能车的存储器密度提高四倍或更多。 此外，可以防止由于使用多个存储器芯片而在常规智能卡制造过程中遇到的问题或测试过程。

公开(公告)号：USD445797S1

公开(公告)日：2001-07-31

申请号：US29122561

申请日：2000-04-28

Applicant: Joon-Ki Lee ,  Ki-Won Choi ,  Young-Shin Kwon

Designer： Joon-Ki Lee ,  Ki-Won Choi ,  Young-Shin Kwon

公开(公告)号：US09679943B2

公开(公告)日：2017-06-13

申请号：US14710740

申请日：2015-05-13

Applicant: Jong Chul Park ,  Shin Jae Kang ,  Shin Kwon ,  Kyung Rae Byun

Inventor： Jong Chul Park ,  Shin Jae Kang ,  Shin Kwon ,  Kyung Rae Byun

IPC: H01L43/08 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/10

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

公开(公告)号：US20160104745A1

公开(公告)日：2016-04-14

申请号：US14710740

申请日：2015-05-13

Applicant: Jong Chul PARK ,  Shin Jae KANG ,  Shin KWON ,  Kyung Rae BYUN

Inventor： Jong Chul PARK ,  Shin Jae KANG ,  Shin KWON ,  Kyung Rae BYUN

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/10

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

Abstract translation: 半导体器件可以包括第一磁性层，其包括构成多个存储器单元并且在衬底上彼此间隔开的多个第一区域，以及包围多个第一区域并与第一区域电隔离的第二区域， 设置在第一磁性层上的隧道势垒层，以及设置在隧道势垒层上的第二磁性层。

公开(公告)号：US09306156B2

公开(公告)日：2016-04-05

申请号：US14533084

申请日：2014-11-04

Applicant: Eun-Sun Noh ,  Jong-Chul Park ,  Shin Kwon ,  Hyung-Joon Kwon ,  Chae-Lyoung Kim ,  Hye-Ji Yoon

Inventor： Eun-Sun Noh ,  Jong-Chul Park ,  Shin Kwon ,  Hyung-Joon Kwon ,  Chae-Lyoung Kim ,  Hye-Ji Yoon

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures. Each MTJ structure includes a sequentially stacked first magnetic layer pattern, tunnel layer pattern, and second magnetic layer pattern, and each of the MTJ structures contacts a corresponding one of the lower electrodes.

Abstract translation: 在制造MRAM器件的方法中，第一牺牲层，蚀刻停止层和第二牺牲层依次形成在衬底上，然后被部分蚀刻以形成通过其的开口。 形成下电极以填充开口。 去除第一和第二牺牲层和蚀刻停止层的部分以分别形成围绕下部电极的侧壁的上部的蚀刻停止层图案。 在蚀刻停止层图案之间形成上部绝缘层图案，以在下部电极之间部分地限定气垫。 形成第一磁性层，隧道势垒层，第二磁性层和上电极层，并被蚀刻以形成多个磁性隧道结（MTJ）结构。 每个MTJ结构包括顺序堆叠的第一磁性层图案，隧道层图案和第二磁性层图案，并且每个MTJ结构接触相应的一个下部电极。