公开(公告)号：US07917882B2

公开(公告)日：2011-03-29

申请号：US11976713

申请日：2007-10-26

申请人： Avishek Panigrahi ,  Soumya Banerjee ,  Thomas Stephen Chanak, Jr.

发明人： Avishek Panigrahi ,  Soumya Banerjee ,  Thomas Stephen Chanak, Jr.

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.

摘要翻译： 本发明提供了一种自动数字电路设计工具，其减少或消除由于固有时钟信号偏斜引起的不利时序约束及其应用。 在一个实施例中，根据本发明的自动设计工具生成包括时钟信号发生器，控制逻辑，使能逻辑和至少一个时钟门控器的时钟系统。 时钟信号发生器使用缓冲时钟树生成分配给数字电路的各个逻辑块的时钟信号。 使能逻辑从控制逻辑接收输入值，并向时钟门控器提供控制信号。 使能时钟时钟允许时钟信号通过多个寄存器。 提供早期时钟信号以在控制逻辑中注册，这允许在仍然满足时序约束的情况下增加时钟频率。

公开(公告)号：US20090113365A1

公开(公告)日：2009-04-30

申请号：US11976713

申请日：2007-10-26

申请人： Avishek Panigrahi ,  Soumya Banerjee ,  Thomas Stephen Chanak, JR.

发明人： Avishek Panigrahi ,  Soumya Banerjee ,  Thomas Stephen Chanak, JR.

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.

摘要翻译： 本发明提供了一种自动数字电路设计工具，其减少或消除由于固有时钟信号偏斜引起的不利时序约束及其应用。 在一个实施例中，根据本发明的自动设计工具生成包括时钟信号发生器，控制逻辑，使能逻辑和至少一个时钟门控器的时钟系统。 时钟信号发生器使用缓冲时钟树生成分配给数字电路的各个逻辑块的时钟信号。 使能逻辑从控制逻辑接收输入值，并向时钟门控器提供控制信号。 使能时钟时钟允许时钟信号通过多个寄存器。 提供早期时钟信号以在控制逻辑中注册，这允许在仍然满足时序约束的情况下增加时钟频率。

公开(公告)号：US20090113180A1

公开(公告)日：2009-04-30

申请号：US12346652

申请日：2008-12-30

申请人： Soumya Banerjee ,  Michael Gottlieb Jensen

发明人： Soumya Banerjee ,  Michael Gottlieb Jensen

IPC分类号： G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3814

摘要： A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities.

摘要翻译： 公开了并行执行N线程指令的多线程微处理器中的提取指导者。 N线程请求从指令高速缓存获取指令。 在给定的选择周期中，某些线程可能没有请求获取指令。 提取指导器包括用于以循环方式选择线程之一以将其提取地址提供给指令高速缓存的电路。 1位左电路通过第二加数旋转地增加第一加数，以产生与第一加数的反相并联的和，以产生指示下一个选择的线程的1-hot向量。 第一个加数是一个N位向量，如果相应的线程请求从指令高速缓存中获取指令，则每个位都为假。 第二个加法是指示最后选择的线程的1-hot向量。 在一个实施例中，以最高优先级选择具有空指令缓冲器的线程; 中间优先级的最后发送但未获取的线程; 所有其他线程的优先级最低。 线程在最高和最低优先级内选择循环。

公开(公告)号：US07490230B2

公开(公告)日：2009-02-10

申请号：US11087063

申请日：2005-03-22

申请人： Michael Gottlieb Jensen ,  Soumya Banerjee

发明人： Michael Gottlieb Jensen ,  Soumya Banerjee

IPC分类号： G06F9/50

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3814

摘要： A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit adds a first addend to a 1-bit left-rotated version of a second addend to generate a sum and a carry-out bit. The circuit includes the carry-out bit as a carry-in bit of the add to generate the sum. The sum is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities.

摘要翻译： 公开了并行执行N线程指令的多线程微处理器中的提取指导者。 N线程请求从指令高速缓存获取指令。 在给定的选择周期中，某些线程可能没有请求获取指令。 提取指导器包括用于以循环方式选择线程之一以将其提取地址提供给指令高速缓存的电路。 该电路将第一个加数添加到第二加数的1位左旋转版本中，以产生一个和和一个进位位。 该电路包括作为加法的进位位的进位位以产生和。 该和与第一个加法项的倒数相加以产生一个1-热向量，指示下一个选择的线程。 第一个加数是一个N位向量，如果相应的线程请求从指令高速缓存中获取指令，则每个位都为假。 第二个加法是指示最后选择的线程的1-hot向量。 在一个实施例中，以最高优先级选择具有空指令缓冲器的线程; 中间优先级的最后发送但未获取的线程; 所有其他线程的优先级最低。 线程在最高和最低优先级内选择循环。

公开(公告)号：US06671752B1

公开(公告)日：2003-12-30

申请号：US09649743

申请日：2000-08-28

申请人： Seetharam Gundu Rao ,  Ashutosh Misra ,  Soumya Banerjee

发明人： Seetharam Gundu Rao ,  Ashutosh Misra ,  Soumya Banerjee

IPC分类号： G06F100

CPC分类号： G06F13/362

摘要： A method, an apparatus, and a computer program product for optimising a bus in a Processor Local Bus (PLB) system are disclosed. A master engine performs a transfer transaction of N bytes of data on the bus of the PLB system. A type of read or write data transfer to be performed by the master engine is determined to optimize operation of the bus in response to a transfer request received asynchronously from a device coupled to the bus. This involves a request type determination function. Data is asynchronously transferred using a FIFO between the device and the bus dependent upon the determined type of transfer.

摘要翻译： 公开了一种用于在处理器局部总线（PLB）系统中优化总线的方法，装置和计算机程序产品。 主引擎在PLB系统的总线上执行N字节数据的传输事务。 确定要由主引擎执行的读或写数据传输的类型，以响应于从耦合到总线的设备异步接收的传送请求来优化总线的操作。 这涉及请求类型确定功能。 数据在设备和总线之间使用FIFO异步传输，具体取决于确定的传输类型。