公开(公告)号：US20090097342A1

公开(公告)日：2009-04-16

申请号：US11870169

申请日：2007-10-10

Applicant: Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

Inventor： Tsu-Wei Tseng ,  Yu-Jen Huang ,  Chun-Hsien Wu ,  Jin-Fu Li ,  Chien-Yuan Pao

IPC: G11C29/12

CPC classification number: G11C29/44 ,  G11C8/16 ,  G11C29/4401 ,  G11C29/808

Abstract: A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.

Abstract translation: 提供了一种用于多端口存储器的内置自修复（BISR）电路及其方法。 该电路包括测试和分析模块（TAM）和耦合到TAM的缺陷定位模块（DLM）。 TAM测试可修复的多端口存储器以产生故障位置，并根据故障位置确定测试是否生成端口特定故障候选。 如果生成了特定于端口的故障候选，则DLM根据故障位置生成缺陷位置，并向TAM提供缺陷位置，以便TAM根据缺陷位置确定如何修复可修复的多端口存储器。 如果在测试中没有生成端口特定的故障候选，则TAM根据故障位置确定如何修复可修复的多端口存储器。

公开(公告)号：USD511333S1

公开(公告)日：2005-11-08

申请号：US29194414

申请日：2003-11-24

Applicant: Te-Hsiung Lai ,  Yu-Jen Huang

Designer： Te-Hsiung Lai ,  Yu-Jen Huang

公开(公告)号：US20050135071A1

公开(公告)日：2005-06-23

申请号：US10737808

申请日：2003-12-18

Applicant: Billy Wang ,  Bill Chang ,  Yu-Jen Huang ,  Chao-Yen Hsieh

Inventor： Billy Wang ,  Bill Chang ,  Yu-Jen Huang ,  Chao-Yen Hsieh

IPC: H01L31/0203 ,  H05K1/14

CPC classification number: H01L31/0203 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/10253 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention provides a package structure of optical sensitive device. The package structure includes a silicon substrate, an optical sensitive device, a supporting pad, a transparent plate and a plurality of conductive wires. The optical sensitive device is positioned on the silicon substrate, and the transparent plate is fixedly positioned on the supporting pad and corresponds to the optical sensitive area of the optical sensitive device. The transparent plate can be positioned on the substrate, and the electrical wires are electrically connected between the optical sensitive device and the substrate. A molding material is applied the periphery of the optical sensitive device and the substrate to prevent the electrical wires from exposed and damaged, thereby resulting in virtually eliminating particle containment

Abstract translation: 本发明提供一种光敏元件的封装结构。 封装结构包括硅衬底，光敏器件，支撑衬垫，透明板和多根导电线。 光敏元件位于硅基板上，透明板固定地位于支撑垫上，对应于光敏元件的光敏区域。 透明板可以位于基板上，电线电连接在光敏元件和基板之间。 在光敏元件和基板的外围施加成型材料，以防止电线暴露和损坏，从而实际上消除了颗粒容纳物