公开(公告)号：US11194574B2

公开(公告)日：2021-12-07

申请号：US16521663

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Miles Robert Dooley ,  Balaji Vijayan ,  Huzefa Moiz Sanjeliwala ,  Abhishek Raja ,  Sharmila Shridhar

IPC: G06F9/30

Abstract: An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.

公开(公告)号：US10719453B1

公开(公告)日：2020-07-21

申请号：US16374018

申请日：2019-04-03

Applicant: Arm Limited

Inventor： Abhishek Raja

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/02 ,  G06F12/0802

Abstract: Each entry of a set associative address translation cache (ATC) stores address translation data (ATD) used by processing circuitry when converting a virtual address into a corresponding physical address. The processing circuitry operates in multiple contexts, and each entry has an associated context identifier identifying the context to which the ATD therein applies. A masking structure comprises at least one mask storage and, for each mask storage, an associated context storage. Each mask storage provides a mask field for each set of the ATC. Control circuitry responds to a maintenance request, specifying a given context and requiring a maintenance operation to be performed in respect of each entry of the ATC that stores ATD applying to the given context, by setting each mask field in a selected mask storage, storing an indication of the given context in the associated context storage, and issuing a response to a request source.

公开(公告)号：US10649907B2

公开(公告)日：2020-05-12

申请号：US15928165

申请日：2018-03-22

Applicant: Arm Limited

Inventor： Abhishek Raja

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/10 ,  G06F12/1045 ,  G06F12/1036 ,  G06F12/126 ,  G06F8/65

Abstract: An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element. Allocation circuitry is responsive to receipt of obtained address translation data for a specified virtual address, to allocate the obtained address translation data into an entry of a selected set of the address translation cache, where the selected set is identified using a subset of bits of the specified virtual address chosen in dependence on a final page size associated with the obtained address translation data. Filter circuitry is provided having a plurality of filter entries, and is responsive to detecting that a splinter condition exists for the obtained address translation data, to indicate in a chosen filter entry that the splinter condition has been detected for the specified item of supervised software that is associated with the obtained address translation data. The splinter condition exists when a first stage page size used in the multi-stage translation process exceeds the final page size. Maintenance circuitry is then responsive to a page invalidate request associated with an item of supervised software, to reference the filter circuitry to determine which entries of the address translation cache need to be checked in order to process the page invalidate request, in dependence on whether a filter entry of the filter circuitry indicates presence of the splinter condition for that item of supervised software.

公开(公告)号：US10191853B2

公开(公告)日：2019-01-29

申请号：US15290039

申请日：2016-10-11

Applicant: ARM LIMITED

Inventor： Abhishek Raja

IPC: G06F12/1009 ,  G06F12/1027

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria. Each descriptor comprises physical address data and attribute data identifying a plurality of attributes, and the attribute match criteria allows the plurality of descriptors to have different values for a first subset of attributes when determining that the attribute match criteria is met. When the predetermined criteria are met, coalesced address translation data is generated from the plurality of descriptors and that coalesced address translation data is then stored in the selected entry. Otherwise, if the predetermined criteria is not met, address translation data is merely generated from the descriptor identified using the virtual address, and that address translation data is then stored in the selected entry. Such an approach significantly increases the effective capacity and performance of the address translation cache.