公开(公告)号：US11188330B2

公开(公告)日：2021-11-30

申请号：US16324239

申请日：2017-08-14

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  François Christopher Jacques Botman

IPC: G06F9/30 ,  G06F15/80 ,  G06F7/544 ,  G06F17/16

Abstract: An apparatus comprises processing circuitry, a number of vector register and a number of scalar registers. An instruction decoder is provided which supports decoding of a vector multiply-add instruction specifying at least one vector register and at least one scalar register. In response to the vector multiply-add instruction, the decoder controls the processing circuitry to perform a vector multiply-add instruction in which each lane of processing generates a respective result data element corresponding to a sum of difference of a product value and an addend value, with the product value comprising the product of a respective data element of a first vector value and a multiplier value. In each lane of processing at least one of the multiplier value and the addend value is specified as a portion of a scalar value stored in a scalar register.

公开(公告)号：US10162633B2

公开(公告)日：2018-12-25

申请号：US15494911

申请日：2017-04-24

Applicant: ARM LIMITED

Inventor： François Christopher Jacques Botman ,  Thomas Christopher Grocutt

IPC: G06F9/30

Abstract: An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.