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公开(公告)号：US20190065188A1
公开(公告)日：2019-02-28
申请号：US16154517
申请日：2018-10-08
Applicant: ALTERA CORPORATION
Inventor： David Shippy , Martin Langhammer , Jeffrey Eastlack
Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
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公开(公告)号：US20180321909A1
公开(公告)日：2018-11-08
申请号：US16039029
申请日：2018-07-18
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06F7/4876 , G06F7/485 , G06F2207/3816 , G06F2207/382 , G06F2207/483
Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.
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公开(公告)号：US10110233B2
公开(公告)日：2018-10-23
申请号：US15190716
申请日：2016-06-23
Applicant: Altera Corporation
Inventor： Martin Langhammer
IPC: G06F17/50 , H03K19/177 , G06F15/82
Abstract: A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.
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公开(公告)号：US09966933B1
公开(公告)日：2018-05-08
申请号：US15161210
申请日：2016-05-21
Applicant: Altera Corporation
Inventor： Volker Mauer , Martin Langhammer
CPC classification number: H03H17/0248 , H03H17/06 , H03H2220/04 , H03H2220/06
Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.
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公开(公告)号：US20180052661A1
公开(公告)日：2018-02-22
申请号：US15242923
申请日：2016-08-22
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06F7/4876 , G06F7/485 , G06F2207/3816 , G06F2207/382 , G06F2207/483
Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.
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公开(公告)号：US20170250713A1
公开(公告)日：2017-08-31
申请号：US15054395
申请日：2016-02-26
Applicant: Altera Corporation
Inventor： Martin Langhammer , Sami Mumtaz , Simon Finn
CPC classification number: H03M13/1515 , H03M13/159 , H03M13/616 , H03M13/617
Abstract: The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.
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公开(公告)号：US09613232B1
公开(公告)日：2017-04-04
申请号：US14880633
申请日：2015-10-12
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06G7/16 , G06F7/44 , G06F7/483 , G06F7/52 , G06F7/5443 , G06G7/14 , H03H17/06 , H03H2220/04 , H03H2220/06
Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.
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公开(公告)号：US09600278B1
公开(公告)日：2017-03-21
申请号：US13941847
申请日：2013-07-15
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06F9/3001 , G06F7/483 , G06F7/509 , G06F7/5443 , H03K19/17732 , H03K19/17744
Abstract: A specialized processing block on a programmable integrated circuit device includes a first floating-point arithmetic operator stage, and a floating-point adder stage having at least one floating-point binary adder. Configurable interconnect within the specialized processing block routes signals into and out of each of the first floating-point arithmetic operator stage and the floating-point adder stage. The block has a plurality of block inputs, at least one block output, a direct-connect input for connection to a first other instance of the specialized processing block, and a direct-connect output for connection to a second other instance of the specialized processing block. A plurality of instances of the specialized processing block are together configurable as a binary or ternary recursive adder tree.
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公开(公告)号：US09552190B1
公开(公告)日：2017-01-24
申请号：US15133363
申请日：2016-04-20
Applicant: Altera Corporation
Inventor： Martin Langhammer , Bogdan Pasca
CPC classification number: G06F7/49915 , G06F7/48 , G06F7/483 , G06F7/49957
Abstract: In accordance with some embodiments, a floating point number datapath circuitry, e.g., within an integrated circuit programmable logic device is provided. The datapath circuitry may be used for computing a rounded absolute value of a mantissa of a floating point number. The floating point datapath circuitry may have only a single adder stage for computing a rounded absolute value of a mantissa of the floating point number based on one or more bits of an unrounded mantissa of the floating point number. The unrounded and rounded mantissas may include a sign bit, a sticky bit, a round bit, and/or a least significant bit, and/or other bits. The unrounded mantissa may be in a format that includes negative numbers (e.g., 2's complement) and the rounded mantissa may be in a format that may include a portion of the floating point number represented as a positive number, (e.g., signed magnitude).
Abstract translation: 根据一些实施例，提供浮点数数据路径电路，例如在集成电路可编程逻辑器件内。 数据路径电路可用于计算浮点数的尾数的舍入绝对值。 浮点数据路径电路可以仅具有单个加法器级，用于基于浮点数的未被四舍五入的尾数的一个或多个位来计算浮点数的尾数的舍入绝对值。 未被四舍五入的尾数可以包括符号位，粘性位，圆比特和/或最低有效位和/或其他位。 未包围的尾数可以是包括负数（例如，2的补码）的格式，并且舍入的尾数可以是可以包括表示为正数的浮点数的一部分（例如，有符号的大小）的格式。
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公开(公告)号：US09552189B1
公开(公告)日：2017-01-24
申请号：US14497250
申请日：2014-09-25
Applicant: Altera Corporation
Inventor： Martin Langhammer , Bogdan Pasca
CPC classification number: G06F7/483 , G06F7/49915 , G06F7/556
Abstract: Circuitry that performs floating-point operations on an integrated circuit is provided. The circuitry may execute a floating-point operation by decomposing the floating-point operation into multiple steps and decomposing the floating-point number on which to perform the floating-point operation into multiple portions. The circuitry may include storage circuits that store at least some results of the multiple steps, and memory access operations may be performed using some portions of the floating-point number. The circuitry may use arithmetic floating-point and arithmetic fixed-point circuits to implement Taylor series expansion circuits that may perform a subset of the multiple steps, thereby reducing the complexity of the subset of these steps.
Abstract translation: 提供了在集成电路上执行浮点运算的电路。 电路可以通过将浮点运算分解成多个步骤并将将浮点运算的浮点数分解成多个部分来执行浮点运算。 电路可以包括存储多个步骤的至少一些结果的存储电路，并且可以使用浮点数的一些部分来执行存储器访问操作。 电路可以使用算术浮点和算术定点电路来实现可以执行多个步骤的子集的泰勒级数扩展电路，从而降低这些步骤的子集的复杂性。
