公开(公告)号：US20130040454A1

公开(公告)日：2013-02-14

申请号：US13205063

申请日：2011-08-08

申请人： Cyril Cabral, JR. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P. Rodbell

IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/302

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76828 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

摘要翻译： 提供了一种通过退火工艺改性硅基技术的化学或微结构的方法。 该方法包括将反应性材料层沉积在选定的互连附近，点燃反应性材料层，以及通过从点燃的反应性材料层传递的热量使互连件退火。 该方法还可以结合硅化物/硅界面以及硅基技术的区域来实现。

公开(公告)号：US20120009771A1

公开(公告)日：2012-01-12

申请号：US12833272

申请日：2010-07-09

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

公开(公告)号：US06878624B1

公开(公告)日：2005-04-12

申请号：US10674645

申请日：2003-09-30

申请人： John Bruley ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Tina J. Wagner ,  Yun Yu Wang ,  Horati S. Wildman ,  Wong Kwong Hon

发明人： John Bruley ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Tina J. Wagner ,  Yun Yu Wang ,  Horati S. Wildman ,  Wong Kwong Hon

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/76856 ,  H01L29/665

摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

摘要翻译： 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。 因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

公开(公告)号：US06777298B2

公开(公告)日：2004-08-17

申请号：US10172649

申请日：2002-06-14

申请人： Ronnen A. Roy ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Kam-Leung Lee

发明人： Ronnen A. Roy ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Kam-Leung Lee

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/324 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  Y10S438/924

摘要： In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.

摘要翻译： 在本发明的一个实施例中，形成源极和漏极区以及源极和漏极接触区域。 此后形成源极和漏极延伸区域。 在另一个实施例中，形成升高的源极和漏极区以及源极和漏极延伸区。 此后，源极和漏极接触区域形成在高达约600℃的温度和高达约1分钟的退火时间。

公开(公告)号：US06436823B1

公开(公告)日：2002-08-20

申请号：US09679738

申请日：2000-10-05

申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。

公开(公告)号：US08658461B2

公开(公告)日：2014-02-25

申请号：US13566050

申请日：2012-08-03

申请人： Cyril Cabral, Jr. ,  Josephine B. Chang ,  Alfred Grill ,  Michael A. Guillorn ,  Christian Lavoie ,  Eugene J. O'Sullivan

发明人： Cyril Cabral, Jr. ,  Josephine B. Chang ,  Alfred Grill ,  Michael A. Guillorn ,  Christian Lavoie ,  Eugene J. O'Sullivan

IPC分类号： H01L51/40

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/16 ,  H01L29/1602 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/105

摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

公开(公告)号：US08101518B2

公开(公告)日：2012-01-24

申请号：US12136885

申请日：2008-06-11

申请人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 在退火步骤A期间，与绝缘材料（例如SiO 2和Si 3 N 4）直接接触的金属不会转化为金属合金硅化物接触。然后进行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属 。

公开(公告)号：US07544610B2

公开(公告)日：2009-06-09

申请号：US10935497

申请日：2004-09-07

申请人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral, Jr. ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/477 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 在绝缘材料如SiO 2和Si 3 N 4中直接接触的金属在退火步骤期间不会转化为金属合金硅化物接触。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US07498640B2

公开(公告)日：2009-03-03

申请号：US10437930

申请日：2003-05-15

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6653 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66507 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

公开(公告)号：US07410852B2

公开(公告)日：2008-08-12

申请号：US11408522

申请日：2006-04-21

申请人： Scott D. Allen ,  Cyril Cabral, Jr. ,  Kevin K. Dezfulian ,  Sunfei Fang ,  Brian J. Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement H. Wann ,  Huilong Zhu

发明人： Scott D. Allen ,  Cyril Cabral, Jr. ,  Kevin K. Dezfulian ,  Sunfei Fang ,  Brian J. Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement H. Wann ,  Huilong Zhu

IPC分类号： H01L21/8234 ,  H01L21/42

CPC分类号： H01L21/268 ,  H01L21/2686 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/324 ,  H01L29/517 ,  H01L29/665

摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。