公开(公告)号：US20100171180A1

公开(公告)日：2010-07-08

申请号：US12349974

申请日：2009-01-07

申请人： Da Zhang ,  Voon-Yew Thean

发明人： Da Zhang ,  Voon-Yew Thean

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor process and apparatus includes forming PMOS transistors (90) with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer (91, 136) on or adjacent to sidewalls of the PMOS gate structure as either a hydrogen-rich implant sidewall spacer (91) or as a post-silicide hydrogen-rich implant sidewall spacer (136), where the hydrogen-rich dielectric layer acts as a hydrogen source for passivating channel surface defectivity under the PMOS gate structure.

摘要翻译： 半导体工艺和装置包括通过在PMOS栅极结构的侧壁上或邻近PMOS栅结构的侧壁上形成富氢的氮化硅层（91,136）来形成在沟道区中具有增强的空穴迁移率的PMOS晶体管（90） 植入侧壁间隔物（91）或作为后硅化物富氢植入物侧壁间隔物（136），其中富氢介电层作为用于钝化PMOS栅极结构下的通道表面缺陷的氢源。

公开(公告)号：US20090289280A1

公开(公告)日：2009-11-26

申请号：US12125853

申请日：2008-05-22

申请人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

发明人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor process and apparatus includes forming channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

摘要翻译： 半导体工艺和装置包括通过外延生长双轴向应力的硅锗沟道区域层（22）来形成具有增强的晶体管沟道区中的空穴迁移率的<100>沟道取向PMOS晶体管（34），单独或与 在形成覆盖在沟道区域层上的PMOS栅极结构（36）之前，然后在PMOS栅极结构上沉积中性（53）或压缩（55）接触蚀刻停止层之后的底层碳化硅层（86）。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

公开(公告)号：US20080014688A1

公开(公告)日：2008-01-17

申请号：US11428953

申请日：2006-07-06

申请人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Da Zhang

发明人： Voon-Yew Thean ,  Bich-Yen Nguyen ,  Da Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

摘要翻译： 半导体制造工艺包括掩蔽半导体晶片的第一区域（例如，NMOS区域），例如双轴拉伸应变绝缘体上硅（SOI）晶片，并在第二晶片区域的源/漏区域中产生凹陷，例如 ，PMOS区域。 然后将晶片在促进硅迁移的环境中退火。 源极/漏极凹槽用源极/漏极结构填充，例如通过外延生长。 退火环境可以包括保持在约800至1000℃范围内的温度的含氢物质，例如H 2 H 2或GeH 2 H 2。第二区域 可以是硅，并且源极/漏极结构可以是硅锗。 创建凹槽可以包括用第一蚀刻工艺创建浅凹槽，执行非晶化注入以产生非晶层，执行惰性环境退火以使非晶层重结晶，以及用第二蚀刻工艺加深浅凹槽。

公开(公告)号：US07282415B2

公开(公告)日：2007-10-16

申请号：US11092291

申请日：2005-03-29

申请人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

发明人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

摘要翻译： 通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。 在控制电极的侧壁附近形成绝缘层。 注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下 半导体器件。 第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。 在第一和第二沟槽内形成有相对于半导体衬底具有不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。

公开(公告)号：US08592625B2

公开(公告)日：2013-11-26

申请号：US12811418

申请日：2008-01-02

申请人： Jiankang Xu ,  Da Zhang ,  Meiqi Ye ,  Jie Chen ,  Yongbing Guo ,  Yongjiang Hu

发明人： Jiankang Xu ,  Da Zhang ,  Meiqi Ye ,  Jie Chen ,  Yongbing Guo ,  Yongjiang Hu

IPC分类号： C07C227/36

CPC分类号： C07C227/34 ,  C07C229/08

摘要： The present invention relates to a process for resolving S-3-(Aminomethyl)-5-methylhexanoic acid, which adopts benzoyl-L-glutamic acid, 4-methyl benzoyl-L-glutamic acid, benzene sulfonyl-L-glutamic acid or 4-methyl benzene sulfonyl-L-glutamic acid as a resolution agent to make a first resolution to racemic 3-aminomethyl-5-methylhexanoic acid, and adopts the resolution agent same to that of the first resolution to make a second resolution to the first resolution product to obtain the second resolution product, thus the resolution salt product is obtained, and further hydrolyzed by an acid, the resolution agent is extracted to be separated, the pH is adjusted to be neutral, the product S-3-(Aminomethyl)-5-methylhexanoic acid, i.e. the pregabalin, is then precipitated by distillation, therefore the present invention has the characteristics of polluting the environment slightly, high efficiency and stability, simpleness and practicality, producing product with high purity and a low production cost, and is suitable for large-scale production.

摘要翻译： 本发明涉及一种分离S-3-（氨基甲基）-5-甲基己酸的方法，该方法采用苯甲酰基-L-谷氨酸，4-甲基苯甲酰基-L-谷氨酸，苯磺酰基-L-谷氨酸或4 甲基苯磺酰基-L-谷氨酸作为拆分剂，首先拆分为外消旋的3-氨基甲基-5-甲基己酸，并采用与第一分辨率相同的分解剂，以第一分辨率作第二分辨率 得到第二分解产物，得到分解盐产物，并进一步用酸水解，提取分离剂分离，将pH调节为中性，产物S-3-（氨基甲基） - 5-甲基己酸，即普瑞巴林，然后通过蒸馏沉淀，因此本发明具有污染环境的特点，效率高，稳定性，简便性和实用性，生产高纯度，低产品的产品 离子成本，适合大规模生产。

公开(公告)号：US20110098502A1

公开(公告)日：2011-04-28

申请号：US12811418

申请日：2008-01-01

申请人： Jiankang Xu ,  Da Zhang ,  Meiqi Ye ,  Jie Chen ,  Yongbing Guo ,  Yongjiang Hu

发明人： Jiankang Xu ,  Da Zhang ,  Meiqi Ye ,  Jie Chen ,  Yongbing Guo ,  Yongjiang Hu

IPC分类号： C07C227/36

CPC分类号： C07C227/34 ,  C07C229/08

摘要： The present invention relates to a process for resolving S-3-(Aminomethyl)-5-methylhexanoic acid, which adopts benzoyl-L-glutamic acid, 4-methyl benzoyl-L-glutamic acid, benzene sulfonyl-L-glutamic acid or 4-methyl benzene sulfonyl-L-glutamic acid as a resolution agent to make a first resolution to racemic 3-aminomethyl-5-methylhexanoic acid, and adopts the resolution agent same to that of the first resolution to make a second resolution to the first resolution product to obtain the second resolution product, thus the resolution salt product is obtained, and further hydrolyzed by an acid, the resolution agent is extracted to be separated, the pH is adjusted to be neutral, the product S-3-(Aminomethyl)-5-methylhexanoic acid, i.e. the pregabalin, is then precipitated by distillation, therefore the present invention has the characteristics of polluting the environment slightly, high efficiency and stability, simpleness and practicality, producing product with high purity and a low sproduction cost, and is suitable for large-scale production.

摘要翻译： 本发明涉及一种分离S-3-（氨基甲基）-5-甲基己酸的方法，该方法采用苯甲酰基-L-谷氨酸，4-甲基苯甲酰基-L-谷氨酸，苯磺酰基-L-谷氨酸或4 甲基苯磺酰基-L-谷氨酸作为拆分剂，首先拆分为外消旋的3-氨基甲基-5-甲基己酸，并采用与第一分辨率相同的分解剂，以第一分辨率作第二分辨率 得到第二分解产物，得到分解盐产物，并进一步用酸水解，提取分离剂分离，将pH调节为中性，产物S-3-（氨基甲基） - 然后通过蒸馏沉淀5-甲基己酸，即普瑞巴林，因此本发明具有轻微，高效和稳定，简单和实用的污染环境的特点，生产高纯度和低产量的产品 成本高，适合大规模生产。

公开(公告)号：US08643217B2

公开(公告)日：2014-02-04

申请号：US12674936

申请日：2007-12-26

申请人： Thomas Gietzold ,  Jeffrey J. Burchill ,  Da Zhang ,  Weiqian Hu

发明人： Thomas Gietzold ,  Jeffrey J. Burchill ,  Da Zhang ,  Weiqian Hu

IPC分类号： H02J3/00

CPC分类号： H02P9/02 ,  Y10T307/675

摘要： An apparatus and method for boosting output of a generator set are provided. The output of the generator set is connected to an electrical load. The apparatus includes an energy storage unit, and a power-electronic unit. The energy storage unit uses batteries and capacitors to store electric energy. The power-electronic unit measures an electrical parameter of the output of the generator set. Based on the measured electrical parameter and a predefined criterion, the power-electronic unit determines additional energy required by the electrical load. Thereafter, the power-electronic unit supplies the additional energy to the electrical load. The additional energy is drawn from the energy storage unit.

摘要翻译： 提供了一种用于提升发电机组的输出的装置和方法。 发电机组的输出连接到电气负载。 该装置包括能量存储单元和电力电子单元。 储能单元使用电池和电容器来储存电能。 电力电子单元测量发电机组输出的电气参数。 基于测量的电参数和预定标准，功率电子单元确定电负载所需的附加能量。 此后，电力电子单元向电负载提供额外的能量。 额外的能量从能量存储单元中抽出。

公开(公告)号：US07795089B2

公开(公告)日：2010-09-14

申请号：US11680219

申请日：2007-02-28

申请人： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

发明人： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772

摘要： A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

摘要翻译： 在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。 第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。 在第一和第二区域上形成第一绝缘层。 第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。 从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。 半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。 在凹部中外延生长半导体材料。 去除第一绝缘层的剩余部分。

公开(公告)号：US07538002B2

公开(公告)日：2009-05-26

申请号：US11361171

申请日：2006-02-24

申请人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

发明人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

公开(公告)号：US07494856B2

公开(公告)日：2009-02-24

申请号：US11393340

申请日：2006-03-30

申请人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78684

摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

摘要翻译： 半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 可以使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿式蚀刻来蚀刻源极/漏极区域。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。