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    System and method of automating the addition of programmable breakpoint hardware to design models
    21.
    发明申请
    System and method of automating the addition of programmable breakpoint hardware to design models 审中-公开
    将可编程断点硬件自动添加到设计模型的系统和方法

    公开(公告)号：US20070005323A1

    公开(公告)日：2007-01-04

    申请号：US11171760

    申请日：2005-06-30

    申请人： Aaron Patzer ,  Joseph Perrie ,  Steven Roberts ,  Todd Swanson

    发明人： Aaron Patzer ,  Joseph Perrie ,  Steven Roberts ,  Todd Swanson

    IPC分类号： G06F17/50

    CPC分类号： G01R31/319 ,  G01R31/318357 ,  G01R31/318364 ,  G01R31/31901 ,  G06F17/5022

    摘要： Hardware logic for generating breakpoint signals based on state changes in observed (“tagged”) hardware resource of a design under test is automatically generated and added to the simulation model of the design under test. These breakpoints halt simulation when a user programmable event, such as an assertion, test-case failure, or trigger occurs. Allowing the end-user to define the register values used in comparison to or timing of tagged resources, results in breakpoints that can be created, changed, enabled, or disabled without rebuilding the simulation model. Because the breakpoint logic is in-circuit, it takes full advantage of the acceleration made possible by hardware simulators, while providing an interactive environment for both functional hardware verification and software development on the simulated hardware mode.

    摘要翻译： 根据被测设计的被观察（“标记”）硬件资源的状态变化产生断点信号的硬件逻辑被自动生成并添加到被测设计的仿真模型中。 当用户可编程事件（如断言，测试用例故障或触发器）发生时，这些断点将停止仿真。 允许最终用户定义与标记资源相比较或定时使用的寄存器值，导致可以创建，更改，启用或禁用的断点，而无需重建仿真模型。 由于断点逻辑是电路中的，它充分利用硬件仿真器可能实现的加速，同时为模拟硬件模式下的功能硬件验证和软件开发提供了一个交互式环境。

    System and method for test generation for system level verification using parallel algorithms
    22.
    发明申请
    System and method for test generation for system level verification using parallel algorithms 有权
    使用并行算法进行系统级验证的测试生成系统和方法

    公开(公告)号：US20060276998A1

    公开(公告)日：2006-12-07

    申请号：US11146987

    申请日：2005-06-06

    申请人： Sanjay Gupta ,  Steven Roberts ,  Christopher Spandikow

    发明人： Sanjay Gupta ,  Steven Roberts ,  Christopher Spandikow

    IPC分类号： G06F15/00

    CPC分类号： G06F11/263

    摘要： A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

    摘要翻译： 提供了一种使用并行算法进行系统级验证的测试生成系统和方法。 本发明通过利用并行算法的可扩展性同时允许数据集着色和预期结果检查来生成用于系统级测试的测试模式。 基于被测系统的特征，从多个可能的并行算法中选择迭代并行算法。 然后将所选择的并行算法分离成单独的程序语句以供多个处理器执行。 执行所选算法的串行版本以产生一组预期结果。 然后运行所选算法的设计的并行版本以生成与一组预期结果进行比较的一组测试结果数据。 如果两组数据匹配，则确定系统正常运行。