公开(公告)号：US06294431B1

公开(公告)日：2001-09-25

申请号：US09547520

申请日：2000-04-12

申请人： Roberto Bez ,  Caterina Riva ,  Giorgio Servalli

发明人： Roberto Bez ,  Caterina Riva ,  Giorgio Servalli

IPC分类号： H01L218247

CPC分类号： H01L27/11521

摘要： A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines. In said step for the definition of the source lines, a process step comprises selectively introducing dopant to form a layer of buried silicon with high concentration of dopant, said layer of buried silicon being formed to such a depth to coincide with the regions of silicon of the underlying field oxide zones, and the introduction of dopant in said active regions of the source lines to superficially contact said layer of buried silicon.

摘要翻译： 一种用于制造具有以矩阵结构的字线和列布置的存储单元的非易失性存储器的过程，其中源极线平行延伸并插入到所述线中，所述源极线由插入到场氧化物区域的有源区形成，所述源极线 过程包括用于定义所述非易失性存储器单元矩阵的所述列的有效区域和所述场氧化物区域的定义的步骤，用于定义所述非易失性存储器单元矩阵的行的后续步骤，以及 以下步骤用于定义所述源线。 在用于定义源极线的所述步骤中，处理步骤包括选择性地引入掺杂剂以形成具有高浓度掺杂剂的掩埋硅层，所述掩埋硅层被形成为与硅的区域重合的深度 底层场氧化物区域，以及在源极线的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层。