公开(公告)号：US07605622B2

公开(公告)日：2009-10-20

申请号：US11478094

申请日：2006-06-30

申请人： Hoon Choi ,  Jae-Jin Lee

发明人： Hoon Choi ,  Jae-Jin Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G06F7/68 ,  H03L7/0805

摘要： A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.

摘要翻译： 具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。 断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。 源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。 相位更新单元基于DLL源时钟信号执行相位更新操作，以输出DLL时钟信号。

公开(公告)号：US07579904B2

公开(公告)日：2009-08-25

申请号：US11623569

申请日：2007-01-16

申请人： Jae-Hyuk Im ,  Jae-Jin Lee

发明人： Jae-Hyuk Im ,  Jae-Jin Lee

IPC分类号： G05F1/10

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4068

摘要： Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.

摘要翻译： 本文公开了一种半导体存储器件的内部电压产生电路，其能够根据存储器件的不同操作模式向存储器件中的列路径和控制逻辑以及数据路径和控制逻辑提供不同电平的电压。 列路径和控制逻辑以及数据路径和控制逻辑在其参与存储器件的当前操作模式时被应用于正常工作电压，而当它们不涉及时具有较低的电压。 因此，本发明具有有效地管理半导体存储器件的内部电压并且减少存储器件的电流泄漏的效果，并且反过来又导致其不必要的功耗。

公开(公告)号：US20090122621A1

公开(公告)日：2009-05-14

申请号：US12170206

申请日：2008-07-09

申请人： Kwang-Myoung Rho ,  Jae-Jin Lee

发明人： Kwang-Myoung Rho ,  Jae-Jin Lee

IPC分类号： G11C7/10 ,  H03K19/0175

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018521

摘要： A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a ground voltage level after a predetermined time.

摘要翻译： 用于控制发送数据的信号线的电路。 该电路包括数据电平控制器，当通过信号线传输的数据的电平改变时，数据电平低于外部电源电压并且在预定时间之后高于接地电压电平 。

公开(公告)号：US07305516B2

公开(公告)日：2007-12-04

申请号：US10877887

申请日：2004-06-25

申请人： Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

发明人： Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/1048 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4096

摘要： There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.

摘要翻译： 提供了一种多端口存储器件，其能够在电流感测型全局数据总线发送/接收结构中的初始操作时防止第一高数据故障现象，而不会导致低数据传输中的问题。 在具有在当前感测型数据发送/接收结构中与全局数据总线交换数据的数据发送/接收块（存储体，端口，全局数据总线连接块等）的多端口存储器件中，初始化开关 用于放电每个全局数据总线，初始化信号发生器控制初始化开关。 初始操作时的第一个高数据故障是由全局数据总线的高预充电电平引起的。 根据本发明，可以在不引起数据传输的问题的情况下降低高预充电水平。

公开(公告)号：US07269041B2

公开(公告)日：2007-09-11

申请号：US11322508

申请日：2005-12-30

申请人： Kyung-Whan Kim ,  Jae-Jin Lee

发明人： Kyung-Whan Kim ,  Jae-Jin Lee

IPC分类号： G11C5/02

CPC分类号： G11C8/16 ,  G11C7/1048 ,  G11C7/1075

摘要： A multi-port memory device that prevents degradation of efficiency of a global data drive by turning off the switches, which do not discharge a global data bus. The multi-port memory device includes a global data bus, a banks, each bank including a transmitter and a receiver; ports, each port including a transmitter and a receiver; switches that operate to selectively connect the receivers of the banks and ports to the global data bus; and a switch signal generator for generating a switch signal in response to data drive pulses inputted to the transmitters of the banks and the ports.

摘要翻译： 一种多端口存储器件，通过关闭不释放全局数据总线的开关来防止全局数据驱动器的效率降低。 多端口存储器件包括全局数据总线，存储体，每个存储体包括发射器和接收器; 端口，每个端口包括发射机和接收机; 用于选择性地将存储体和端口的接收器连接到全局数据总线的开关; 以及开关信号发生器，用于响应于输入到所述存储体和所述端口的发射器的数据驱动脉冲而产生开关信号。

公开(公告)号：US07254087B2

公开(公告)日：2007-08-07

申请号：US11322789

申请日：2005-12-29

申请人： Kyung-Whan Kim ,  Jae-Jin Lee

发明人： Kyung-Whan Kim ,  Jae-Jin Lee

IPC分类号： G11C8/00

CPC分类号： G11C7/1075

摘要： A multi-port memory device improves efficiency of a global data drive by controlling the global data bus to transmit data in a predetermined range. The multi-port memory device includes a global data bus; transmitters and receivers; a termination unit for controlling the global data bus to transmit the data in a range between a first voltage and a second voltage in response to an active mode signal; and a voltage generator for generating the first and the second voltages. The first voltage is higher than a ground voltage and the second voltage is lower than a power supply voltage.

摘要翻译： 多端口存储器件通过控制全局数据总线在预定范围内传输数据来提高全局数据驱动的效率。 多端口存储器件包括全局数据总线; 发射机和接收机; 终端单元，用于响应于活动模式信号，控制全局数据总线在第一电压和第二电压之间的范围内传输数据; 以及用于产生第一和第二电压的电压发生器。 第一电压高于接地电压，第二电压低于电源电压。

公开(公告)号：US20070041258A1

公开(公告)日：2007-02-22

申请号：US11589038

申请日：2006-10-30

申请人： Dong-Keun Kim ,  Jae-Jin Lee

发明人： Dong-Keun Kim ,  Jae-Jin Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/18 ,  G11C2207/105

摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.

摘要翻译： 一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。 半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

公开(公告)号：US07031202B2

公开(公告)日：2006-04-18

申请号：US10744257

申请日：2003-12-22

申请人： Seok-Cheol Yoon ,  Jae-Jin Lee

发明人： Seok-Cheol Yoon ,  Jae-Jin Lee

IPC分类号： G11C11/34

CPC分类号： G11C11/4085 ,  G11C8/08 ,  G11C11/406 ,  G11C2211/4068

摘要： The present relates to a memory device; and, more particularly, to an apparatus and a method for preventing a loss of reliability of data, which are stored in memory cell, at the time of restoring and writing the data. The semiconductor memory device according to the present invention comprises: a high voltage generator for boosting an external voltage level and then for producing a first high voltage level; a pumping control signal generator for issuing a pumping control signal, which is activated in a restore section and a write section, in response to a command signal; a pumping unit for outputting the first high voltage level from the high voltage generator or for boosting the high voltage level in order to generate a second high voltage plus level in response to the pumping control signal from the pumping control signal generator, wherein the second high voltage plus level is higher than the first high voltage level; and a word line driver for driving the word line WL using the first high voltage level and for driving the word line WL using the second high voltage plus level from the pumping unit in the restore and write sections.

摘要翻译： 本发明涉及一种存储装置; 更具体地，涉及在恢复和写入数据时防止存储在存储单元中的数据的可靠性损失的装置和方法。 根据本发明的半导体存储器件包括：高压发生器，用于升高外部电压电平，然后产生第一高电压电平; 泵送控制信号发生器，用于响应于命令信号发出在恢复部分和写入部分中激活的泵送控制信号; 泵送单元，用于从高压发生器输出第一高电压电平或用于升高高电压电平，以便响应于来自泵送控制信号发生器的泵送控制信号产生第二高电压加电平，其中第二高电平 电压加电平高于第一高电压电平; 以及字线驱动器，用于使用第一高电压电平驱动字线WL，并且使用来自恢复和写入部分中的泵送单元的第二高电压加电平来驱动字线WL。

公开(公告)号：US20050249020A1

公开(公告)日：2005-11-10

申请号：US10877888

申请日：2004-06-25

申请人： Kyung-Whan Kim ,  Il-Ho Lee ,  Jae-Jin Lee

发明人： Kyung-Whan Kim ,  Il-Ho Lee ,  Jae-Jin Lee

IPC分类号： G11C11/407 ,  G11C5/06 ,  G11C7/10 ,  G11C8/00 ,  G11C8/16 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/4099

CPC分类号： G11C11/4099 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/4096 ,  G11C2207/2227

摘要： A multi-port memory device capable of preventing the first high data failure at an initial data transmission on a global data bus line according to the present invention includes: a global data bus line including a plurality of bus lines; a plurality of data transmitting and receiving unit including transmitters/receivers, which use a current sensing, for exchanging data into the global data bus line, wherein the receiver in the data transmitting and receiving unit includes resistors for dividing a voltage level; and a variable reference voltage generator for generating reference voltage levels as a receiver reference voltage, by controlling the resistance of the resistors in the receiver, wherein the variable reference voltage generator generates a first reference voltage level in an active mode and generates a second reference voltage level in a standby mode and wherein the first reference voltage level is higher than the second reference voltage level.

摘要翻译： 根据本发明的能够防止在全局数据总线上的初始数据传输时的第一高数据故障的多端口存储器件包括：包括多条总线的全局数据总线; 多个数据发送和接收单元，包括使用电流检测的发送器/接收器，用于将数据交换到全局数据总线中，其中数据发送和接收单元中的接收器包括用于分压电压电平的电阻器; 以及可变参考电压发生器，用于通过控制接收器中的电阻器的电阻来产生参考电压电平作为接收器参考电压，其中可变参考电压发生器在激活模式下产生第一参考电压电平并产生第二参考电压 电平处于待机模式，并且其中第一参考电压电平高于第二参考电压电平。

公开(公告)号：US20050248385A1

公开(公告)日：2005-11-10

申请号：US11016712

申请日：2004-12-21

申请人： Kang-Seol Lee ,  Jae-Jin Lee

发明人： Kang-Seol Lee ,  Jae-Jin Lee

IPC分类号： G11C5/14 ,  H03K3/38

CPC分类号： G11C5/145

摘要： The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

摘要翻译： 本发明提供了一种内部电压提供内部操作所需的最佳驾驶性能的电压供应器。 半导体存储器件的电压供应器包括：内部电压检测装置，用于检测内部电压的电压电平; 时钟振荡装置，用于输出电荷泵送时钟信号; 内部电压控制装置，用于根据数据存取模式或非数据存取模式选择性地控制时钟振荡装置; 以及电荷泵送装置，用于响应于电荷泵送时钟信号，通过泵送电荷来输出内部操作所需的内部电压。