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40 条记录 (耗时 0.036 秒)

    Signal generator with selectable mode control
    22.
    发明申请
    Signal generator with selectable mode control 失效
    具有可选模式控制的信号发生器

    公开(公告)号：US20050242851A1

    公开(公告)日：2005-11-03

    申请号：US10834730

    申请日：2004-04-29

    申请人： Richard Booth ,  Roger Minear ,  Parag Parikh

    发明人： Richard Booth ,  Roger Minear ,  Parag Parikh

    IPC分类号： H03B19/00 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/197

    CPC分类号： H03L7/0996 ,  H03L7/081 ,  H03L7/197

    摘要： A signal generator circuit includes a controller adapted to generate a divide value in accordance with at least a first control signal, and a divider adapted to divide an output signal of the signal generator circuit by the divisor value. The controller is selectively operable in at least one of a plurality of modes in accordance with at least a second control signal. The controller is configured to calculate each of one or more new divide values so as to vary a frequency of the output signal in accordance with at least one of the first and second control signals. The controller is configured to switch between operational modes and/or switch between divide values, the switching between operational modes and/or divide values being performed in such a manner so as to substantially eliminate discontinuities in the frequency of the output signal.

    摘要翻译： 信号发生器电路包括适于根据至少第一控制信号产生分频值的控制器和适于将信号发生器电路的输出信号除以除数值的分频器。 控制器可根据至少第二控制信号以多种模式中的至少一种选择性地操作。 控制器被配置为计算一个或多个新的除法值中的每一个，以便根据第一和第二控制信号中的至少一个来改变输出信号的频率。 控制器被配置为在操作模式之间切换和/或在分频值之间切换，操作模式之间的切换和/或以这样的方式进行分频，以便基本上消除输出信号频率的不连续性。

    Phase locked loop circuit with selectable feedback paths
    26.
    发明授权
    Phase locked loop circuit with selectable feedback paths 有权
    具有可选反馈路径的锁相环电路

    公开(公告)号：US08531222B1

    公开(公告)日：2013-09-10

    申请号：US13079595

    申请日：2011-04-04

    申请人： Barry Britton ,  Richard Booth ,  Phillip L. Johnson ,  Yang Xu ,  Tawei David Li

    发明人： Barry Britton ,  Richard Booth ,  Phillip L. Johnson ,  Yang Xu ,  Tawei David Li

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0802 ,  H03L7/095 ,  H03L7/14 ,  H03L7/18 ,  H03L2207/08

    摘要： A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit. The method also includes switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal if the external circuit is enabled for the normal operation mode.

    摘要翻译： 锁相环（PLL）电路具有可选择的反馈路径。 在一个示例中，操作设备的方法包括通过PLL电路的内部反馈路径传递由该器件的PLL电路提供的时钟信号，以向PLL电路提供第一输入信号，同时至少一个外部电路 在器件的低功耗操作模式下，器件的外部反馈通路被禁止。 该方法还包括在低功率操作模式期间检测第一输入信号和参考信号之间的锁定。 锁定指示时钟信号以在设备的正常操作模式期间使用的频率操作。 该方法还包括使时钟信号通过外部反馈路径以向PLL电路提供第二输入信号。 该方法还包括如果外部电路用于正常操作模式，则从检测第一输入信号和参考信号之间的锁定切换到检测第二输入信号和参考信号之间的锁定。

    Phase interpolator based on an injected passive RLC resonator
    27.
    发明授权
    Phase interpolator based on an injected passive RLC resonator 有权
    基于注入的无源RLC谐振器的相位内插器

    公开(公告)号：US08427217B1

    公开(公告)日：2013-04-23

    申请号：US13434590

    申请日：2012-03-29

    申请人： Gregoire Le Grand de Mercey ,  Richard Booth

    发明人： Gregoire Le Grand de Mercey ,  Richard Booth

    IPC分类号： H03H11/16

    CPC分类号： H03H11/22 ,  H03H11/20

    摘要： A phase interpolation circuit based on injected passive capacitances and an inductance for forming a resonator. The circuit conducts at least a first reference signal having a first phase component and a second reference signal having a second phase component shifted from the first phase component. By selectively switching the first reference signal and/or the second reference signal through one or more capacitances, an interpolated third signal having a third phase component between the first phase component and the second phase component can be generated. An inductor is connected with one or more of the capacitances for forming a resonant circuit to boost the signal level of the interpolated third signal. By utilizing resonance, an improved signal-to-noise ratio may be obtained for the interpolated third signal. An additional amplification stage, secondary to the resonant circuit, may be incorporated for further amplifying the signal level of the interpolated third signal.

    摘要翻译： 基于注入无源电容的相位插值电路和用于形成谐振器的电感。 电路至少传导具有第一相位分量的第一参考信号和具有从第一相位分量偏移的第二相位分量的第二参考信号。 通过通过一个或多个电容选择性地切换第一参考信号和/或第二参考信号，可以产生具有第一相位分量和第二相位分量之间的第三相位分量的内插第三信号。 电感器与一个或多个电容连接，用于形成谐振电路以升高内插第三信号的信号电平。 通过利用谐振，可以获得针对内插的第三信号的改善的信噪比。 可以并入次级谐振电路的附加放大级，用于进一步放大内插第三信号的信号电平。

    Loop filter for use in a phase-locked loop
    30.
    发明申请
    Loop filter for use in a phase-locked loop 有权
    环路滤波器用于锁相环路

    公开(公告)号：US20050219001A1

    公开(公告)日：2005-10-06

    申请号：US10813291

    申请日：2004-03-30

    申请人： Richard Booth

    发明人： Richard Booth

    IPC分类号： H03L7/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/18

    CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/18 ,  H03L2207/06

    摘要： An integrated circuit including at least one loop filter for use in a phase-locked loop, the loop filter including a resistive element and at least one metal-oxide-semiconductor (MOS) transistor configured as a capacitor having a first capacitance associated therewith. The MOS transistor is connected between a voltage source and an input of the loop filter via the resistive element. The loop filter further includes a bias circuit connected to the MOS transistor. The bias circuit is configured for maintaining a substantially constant reference voltage across the MOS transistor, the reference voltage being selected so as to bias the MOS transistor in a designated region of operation. In this manner, the first capacitance is substantially optimized per unit area.

    摘要翻译： 一种集成电路，包括用于锁相环的至少一个环路滤波器，环路滤波器包括电阻元件和配置为具有与其相关联的第一电容的电容器的至少一个金属氧化物半导体（MOS）晶体管。 MOS晶体管通过电阻元件连接在电压源和环路滤波器的输入端之间。 环路滤波器还包括连接到MOS晶体管的偏置电路。 偏置电路被配置为在MOS晶体管两端保持基本上恒定的参考电压，所述参考电压被选择为在指定的操作区域中偏置MOS晶体管。 以这种方式，基本上每单位面积优化第一电容。