公开(公告)号：US08647613B2

公开(公告)日：2014-02-11

申请号：US11886319

申请日：2006-03-10

申请人： Shinji Takeoka ,  Yosuke Okamura ,  Hideo Kanazawa ,  Shuji Hisamoto ,  Kohei Kubota ,  Yosuke Obata

发明人： Shinji Takeoka ,  Yosuke Okamura ,  Hideo Kanazawa ,  Shuji Hisamoto ,  Kohei Kubota ,  Yosuke Obata

IPC分类号： A61K31/787

CPC分类号： A61K9/1272 ,  A61K47/6911

摘要： The present invention has an object of providing a drug carrier capable of controlling in vivo pharmacokinetics. The present invention is directed to a drug carrier comprising a molecular assembly having a drug incorporated therein, and the above object can be achieved by a part of the amphiphilic molecules included in the molecular assembly being released from the molecular assembly by an external environmental change. The present invention utilizes a phenomenon that the hydrophilic-hydrophobic balance of the amphiphilic molecules is shifted toward hydrophilicity by an external environmental change and thus the amphiphilic molecules are freed from the molecular assembly.

摘要翻译： 本发明的目的是提供能够控制体内药代动力学的药物载体。 本发明涉及包含其中并入药物的分子组合物的药物载体，并且上述目的可以通过外部环境变化从分子组合中包含的一部分包含在分子组合中的两亲分子来实现。 本发明利用两亲性分子的亲水疏水性平衡通过外部环境变化向亲水性转移的现象，从而使两亲分子脱离分子组装。

公开(公告)号：US08587076B2

公开(公告)日：2013-11-19

申请号：US13547913

申请日：2012-07-12

申请人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/108 ,  H01L31/119 ,  H01L31/062

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US08253180B2

公开(公告)日：2012-08-28

申请号：US13037831

申请日：2011-03-01

申请人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji Hirase ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US08247873B2

公开(公告)日：2012-08-21

申请号：US12621965

申请日：2009-11-19

申请人： Shinji Takeoka

发明人： Shinji Takeoka

IPC分类号： H01L29/76

CPC分类号： H01L21/823468 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a first MISFET and a second MISFET, wherein the first MISFET includes a semiconductor substrate 100, a first gate insulating film 101a and a first gate electrode 102a formed on the first region of the semiconductor substrate, and first side walls (103a, 120a) formed on the side surface of the first gate electrode 102a, and the second MISFET includes a second gate insulating film 101b and a second gate electrode 102b formed on the second region of the semiconductor substrate 100, and second side walls (103b, 120b) formed on the side surface of the second gate electrode 102b. The width of the first side wall is smaller than the width of the second side wall, and the second side wall includes the second spacer 103b containing a higher concentration of hydrogen than the first spacer 103a.

摘要翻译： 半导体器件包括第一MISFET和第二MISFET，其中第一MISFET包括形成在半导体衬底的第一区域上的半导体衬底100，第一栅极绝缘膜101a和第一栅电极102a以及第一侧壁（103a ，120a），并且第二MISFET包括形成在半导体衬底100的第二区域上的第二栅极绝缘膜101b和第二栅极电极102b，以及第二侧壁（103b， 120b）形成在第二栅电极102b的侧表面上。 第一侧壁的宽度小于第二侧壁的宽度，并且第二侧壁包括含有比第一间隔件103a更高浓度的氢的第二间隔件103b。

公开(公告)号：US20110147857A1

公开(公告)日：2011-06-23

申请号：US13037831

申请日：2011-03-01

申请人： Junji HIRASE ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

发明人： Junji HIRASE ,  Akio Sebe ,  Naoki Kotani ,  Gen Okazaki ,  Kazuhiko Aida ,  Shinji Takeoka

IPC分类号： H01L29/772

CPC分类号： H01L29/4983 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

摘要翻译： 半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。 高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。 位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

公开(公告)号：US07838685B2

公开(公告)日：2010-11-23

申请号：US11919286

申请日：2006-04-27

申请人： Shinji Takeoka ,  Yosuke Obata

发明人： Shinji Takeoka ,  Yosuke Obata

IPC分类号： C07D233/61

CPC分类号： A61K8/44 ,  A61K8/43 ,  A61K8/4946 ,  A61K9/127 ,  A61K9/1272 ,  A61K47/183 ,  A61Q19/00 ,  C07D233/64 ,  C07K5/06086 ,  C07K5/06095 ,  C07K5/06147

摘要： The present invention provides a novel complex lipid having a cationic functional group derived from an amino acid. Namely, the present invention provides a cationic acid amino acid type lipid represented by the following formula: wherein, R1 is a hydrocarbon group having a cationic functional group derived from an amino acid, R2 and R3 are each independently a chain hydrocarbon group, A1 and A2 are each independently a linkage group selected from the group consisting of —COO—, —OCO—, —CONH— and NHCO—, and n is an integer of 2 to 4.

摘要翻译： 本发明提供具有衍生自氨基酸的阳离子官能团的新型复合脂质。 即，本发明提供由下式表示的阳离子酸性氨基酸型脂质：其中，R1为具有来自氨基酸的阳离子官能团的烃基，R2和R3各自独立地为链状烃基，A1和 A2各自独立地为选自-COO-，-OCO-，-CONH-和NHCO-的连接基团，n为2〜4的整数。

公开(公告)号：US20100291672A1

公开(公告)日：2010-11-18

申请号：US12312648

申请日：2007-11-26

申请人： Shinji Takeoka ,  Naoya Takeda ,  Hitoshi Kurumizaka ,  Isao Sakane ,  Namiko Ikegaya ,  Yosuke Obata ,  Syunsuke Saito

发明人： Shinji Takeoka ,  Naoya Takeda ,  Hitoshi Kurumizaka ,  Isao Sakane ,  Namiko Ikegaya ,  Yosuke Obata ,  Syunsuke Saito

IPC分类号： C12N5/07 ,  C07C229/26

CPC分类号： C07C237/22 ,  C07C237/08 ,  C07C237/12 ,  C07K5/021 ,  C07K5/06086 ,  C07K5/0815

摘要： The present invention provides a reagent for introducing a protein or gene into a cell. The reagent of the present invention is, for example, a reagent for introducing a protein or gene into a cell, which comprises a composition comprising a cationic amino acid type lipid represented by the following formula (I)-1: (wherein in formula (I)-1: L is a single bond, —CONH—, or —S—S—; M1 is —(CH2)k— or —(CH2CH2O)k— (wherein k is an integer between 0 and 14); and m1 and m2 are each independently an integer between 11 and 21 (in this regard, when providing a reagent for introducing a gene into a cell, the case where both m1 and m2 are 15 is excluded)).

摘要翻译： 本发明提供了将蛋白质或基因导入细胞的试剂。 本发明的试剂是例如将蛋白质或基因导入细胞的试剂，其包含含有下式（I）-1表示的阳离子型氨基酸型脂质的组合物（式中，式 I）-1：L是单键，-CONH-或-S-S-; M 1是 - （CH 2）k - 或 - （CH 2 CH 2 O）k-（其中k是0和14之间的整数）;和 m1和m2各自独立地为11-21之间的整数（在这方面，当提供用于将基因导入细胞的试剂时，m1和m2均为15的情况除外））。

公开(公告)号：US07732839B2

公开(公告)日：2010-06-08

申请号：US11525011

申请日：2006-09-22

申请人： Akio Sebe ,  Naoki Kotani ,  Shinji Takeoka ,  Gen Okazaki ,  Junji Hirase ,  Kazuhiko Aida

发明人： Akio Sebe ,  Naoki Kotani ,  Shinji Takeoka ,  Gen Okazaki ,  Junji Hirase ,  Kazuhiko Aida

IPC分类号： H01L27/10

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.

摘要翻译： MIS晶体管包括栅电极部分，形成在栅电极部分的侧表面上的绝缘侧壁，源极/漏极区域和形成为覆盖栅电极部分和源极/漏极区域的应力膜。 栅电极部分的上表面的高度小于每个绝缘侧壁的上边缘的高度。 位于栅电极部分的应力膜的第一部分的厚度大于位于源/漏区上的应力膜的第二部分的厚度。

公开(公告)号：US20090298255A1

公开(公告)日：2009-12-03

申请号：US12539203

申请日：2009-08-11

申请人： Tokuhiko TAMAKI ,  Naoki Kotani ,  Shinji Takeoka

发明人： Tokuhiko TAMAKI ,  Naoki Kotani ,  Shinji Takeoka

IPC分类号： H01L21/761 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  Y10S257/903

摘要： A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

摘要翻译： 包括SRAM部分和逻辑电路部分的半导体器件包括：第一n型MIS晶体管，包括第一n型栅极，其形成有插入在SRAM中的半导体衬底的第一元件形成区域上的第一栅极绝缘膜 部分; 以及第二n型MIS晶体管，其包括形成有第二栅极绝缘膜的第二n型栅电极，所述第二栅极绝缘膜插入在所述逻辑电路部分中的所述半导体衬底的第二元件形成区域上。 第一n型栅电极中的第一n型杂质的第一杂质浓度低于第二n型栅极中的第二n型杂质的第二杂质浓度。

公开(公告)号：US20080036010A1

公开(公告)日：2008-02-14

申请号：US11808620

申请日：2007-06-12

申请人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

发明人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  Y10S257/903

摘要： A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

摘要翻译： 包括SRAM部分和逻辑电路部分的半导体器件包括：第一n型MIS晶体管，包括第一n型栅极，其形成有插入在SRAM中的半导体衬底的第一元件形成区域上的第一栅极绝缘膜 部分; 以及第二n型MIS晶体管，其包括形成有第二栅极绝缘膜的第二n型栅电极，所述第二栅极绝缘膜插入在所述逻辑电路部分中的所述半导体衬底的第二元件形成区域上。 第一n型栅电极中的第一n型杂质的第一杂质浓度低于第二n型栅极中的第二n型杂质的第二杂质浓度。