Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
    21.
    发明申请
    Efficient parallel testing of semiconductor devices using a known good device to generate expected responses 失效
    使用已知的良好器件对半导体器件进行有效的并行测试以产生预期响应

    公开(公告)号:US20020175697A1

    公开(公告)日:2002-11-28

    申请号:US10208173

    申请日:2002-07-29

    CPC classification number: G01R31/3193 G01R31/31905

    Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

    Abstract translation: 公开了一种用于测试集成电路器件的系统,其中测试器通过通道与已知的良好器件进行通信。 测试仪 - DUT接口电路用于监视通道,同时测试人员将数据作为测试序列的一部分写入已知的良好设备中的位置。 作为响应,接口电路将数据写入被测设备(DUT)中的每一个中的相应位置。 当测试仪从已知的良好设备(KGD)中的位置读取时,接口电路监视通道,并且响应于从被测设备中的相应位置读取的DUT数据和从KGD获得的预期响应之间的比较。

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