Abstract:
System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a device. The SPI bridge additionally includes a first analog multiplexor control configured to route signals to a circuitry. The SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control.
Abstract:
Systems, methods, and computer-readable media for fault detection are disclosed. At least one controller may identify a plurality of values where each value corresponds to a monitored parameter or a measured parameter. The at least one controller may determine a respective deviation between each of the plurality of values and an expected value, and may further determine whether at least one of the respective deviations exceeds a threshold. Upon a determination that at least one of the respective deviations exceeds the threshold, a fault may be detected. Each of the plurality of values may be associated with a respective device that monitors or measures the value. A detected fault may be associated with the device that monitors or measures the value determined to deviate from the expected value by more than the threshold.