公开(公告)号：US20130139121A1

公开(公告)日：2013-05-30

申请号：US13366756

申请日：2012-02-06

申请人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

发明人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

摘要翻译： 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型使得能够利用一个或多个TSV对插入件进行精确的RC提取，由此提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US08607179B2

公开(公告)日：2013-12-10

申请号：US13366756

申请日：2012-02-06

申请人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

发明人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.