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公开(公告)号：US20190278599A1
公开(公告)日：2019-09-12
申请号：US16422887
申请日：2019-05-24
Applicant: Intel Corporation
Inventor： Kshitij A. DOSHI
IPC: G06F9/30 , G06F11/14 , G06F11/00 , G06F12/0875
Abstract: A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate instruction is to indicate a destination storage location. The processor also includes an execution unit coupled with the decode unit and the at least one memory controller. The execution unit, in response to the persistent commit demarcate instruction, is to store a demarcation value in the destination storage location. The demarcation value may demarcate at least all first store to persistent memory operations that are to have been accepted to memory when the persistent commit demarcate instruction is performed, but which are not necessarily to have been stored persistently, from at least all second store to persistent memory operations that are not yet to have been accepted to memory when the persistent commit demarcate instruction is performed.
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公开(公告)号：US20240111879A1
公开(公告)日：2024-04-04
申请号：US18370137
申请日：2023-09-19
Applicant: Intel Corporation
Inventor： Ned SMITH , Kshitij A. DOSHI , Francesc GUIM BERNAT , Kapil SOOD , Tarun VISWANATHAN
IPC: G06F21/60 , G06F15/173 , H04L9/32
CPC classification number: G06F21/602 , G06F15/17331 , H04L9/3268
Abstract: Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.
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公开(公告)号：US20240080246A1
公开(公告)日：2024-03-07
申请号：US18375934
申请日：2023-10-02
Applicant: Intel Corporation
Inventor： Francesc GUIM BERNAT , Suraj PRABHAKARAN , Kshitij A. DOSHI , Brinda GANESH , Timothy VERRALL
IPC: H04L41/16 , G06N3/04 , G06N5/04 , H04L41/0816 , H04L41/5009 , H04L41/5019 , H04L41/5051
CPC classification number: H04L41/16 , G06N3/04 , G06N5/04 , H04L41/0816 , H04L41/5012 , H04L41/5019 , H04L41/5051
Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.
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24.发明申请
公开(公告)号：US20210288793A1
公开(公告)日：2021-09-16
申请号：US17332733
申请日：2021-05-27
Applicant: Intel Corporation
Inventor： Francesc GUIM BERNAT , Suraj PRABHAKARAN , Kshitij A. DOSHI , Timothy VERRALL
IPC: H04L9/08 , G06F3/06 , G06F9/50 , H04L29/06 , H04L29/08 , G06F16/25 , G06F16/2453 , H04L12/861 , G11C8/12 , G11C29/02 , H04L12/24 , G06F30/34 , G11C29/36 , G11C29/38 , G11C29/44 , G06F16/22 , G06F16/2455 , G06F12/02 , G06F12/14 , G06F13/16 , G06F15/173 , G06F13/40 , G06F13/42 , G06F9/448 , G06F9/28 , G06F15/16 , H04L12/703 , H04L12/743 , H04L12/801 , H04L12/803 , H04L12/935 , H04L12/931 , G06F9/4401 , G06F9/445 , G06F12/06 , G06F16/23 , G06F16/248 , G06F16/901 , G06F16/11
Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.
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25.发明申请
公开(公告)号：US20210255897A1
公开(公告)日：2021-08-19
申请号：US17246441
申请日：2021-04-30
Applicant: Intel Corporation
Inventor： Francesc GUIM BERNAT , Suraj PRABHAKARAN , Daniel RIVAS BARRAGAN , Kshitij A. DOSHI
Abstract: Technologies for opportunistic acceleration overprovisioning for disaggregated architectures that include multiple processors on one or more compute devices. The disaggregated architecture to also include a compute device that includes at least one accelerator device and acceleration management circuitry. The acceleration management circuitry receives a plurality of job execution requests. The acceleration management circuitry to overprovision one or more accelerators by scheduling two or more job execution requests from among the plurality of job execution requests for execution by each accelerator device.
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26.发明申请
公开(公告)号：US20190251034A1
公开(公告)日：2019-08-15
申请号：US16396576
申请日：2019-04-26
Applicant: Intel Corporation
Inventor： Francesc GUIM BERNAT , Dimitrios ZIAKAS , Mark A. SCHMISSEUR , Kshitij A. DOSHI , Kimberly A. MALONE
IPC: G06F12/0888 , G06F12/1027 , G06F12/06 , G06N3/04 , G06F9/50
CPC classification number: G06F12/0888 , G06F9/5016 , G06F9/5061 , G06F12/0607 , G06F12/1027 , G06N3/04
Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
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公开(公告)号：US20190102262A1
公开(公告)日：2019-04-04
申请号：US15721625
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Vadim SUKHOMLINOV , Kshitij A. DOSHI , Tamir D. MUNAFO , Sanjeev N. TRIKA , Urvi PATEL , Rowel S. GARCIA
IPC: G06F11/14
Abstract: A storage controller performs continuous checkpointing. With continuous checkpointing, the information necessary for system rollback is continuously recorded without the need of a specific command. With the rollback information, the system can rollback or restore to any previous state up to a number of previous writes or up to an amount of data. The number of writes or the amount of data that can be restored are configurable.
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公开(公告)号：US20190042339A1
公开(公告)日：2019-02-07
申请号：US16024614
申请日：2018-06-29
Applicant: Intel Corporation
Inventor： Kshitij A. DOSHI , Vadim SUKHOMLINOV
Abstract: Examples include techniques for invocation of a function or service. Examples include receiving a call instruction from an application hosted by a platform to invoke a virtual function provided by a different application. Information included in the call instruction are used to determine how to prepare for and enter an invocation of the call for the virtual function.
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公开(公告)号：US20180165213A1
公开(公告)日：2018-06-14
申请号：US15719491
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Francesc Guim BERNAT , Kshitij A. DOSHI , Robert G. BLANKENSHIP
IPC: G06F12/0884
Abstract: A request is received from a first node over a communication fabric, the request to acquire an access right of a cache line for accessing data stored in a memory location of a memory, the first node being one of a plurality of nodes sharing the memory. In response to the request, a second node is determined based on the cache line that has cached a copy of the data of the cache line in its local memory. A first message is transmitted to the second node over the communication fabric requesting the second node to invalidate the cache line. In response to a response received from the second node indicating that the cache line has been invalidated, a second message is transmitted to the first node over the communication fabric to grant the access right of the cache line to the first node.
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公开(公告)号：US20230138094A1
公开(公告)日：2023-05-04
申请号：US18090255
申请日：2022-12-28
Applicant: Intel Corporation
Inventor： Francesc GUIM BERNAT , Marcos E. CARRANZA , Cesar Ignacio MARTINEZ SPESSOT , Kshitij A. DOSHI , Ned SMITH
IPC: G06F3/06
Abstract: Methods and apparatus for opportunistic memory pools. The memory architecture is extended with logic that divides and tracks the memory fragmentation in each of a plurality of smart devices in two virtual memory partitions: (1) the allocated-unused partition containing memory that is earmarked for (allocated to), but remained un-utilized by the actual workloads running, or, by the device itself (bit-streams, applications, etc.); and (2) the unallocated partition that collects unused memory ranges and pushes them in to an Opportunistic Memory Pool (OMP) which is exposed to the platform's memory controller and operating system. The two partitions of the OMP allow temporary utilization of otherwise unused memory. Under alternate configurations, the total amount of memory resources is presented as a monolithic resource or two monolithic memory resources (unallocated and allocated but unused) available for utilization by the devices and applications running in the platform.
