公开(公告)号：US20180041770A1

公开(公告)日：2018-02-08

申请号：US15483146

申请日：2017-04-10

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Fangwen Fu ,  Satya N. Yedidi ,  Srinivasan Embar Raghukrishnan

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182 ,  H04N19/176

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder comprises at least a fixed function dual hierarchical motion estimation search units, dual integer motion estimation search units, and a fractional motion estimation search unit. Moreover, the hardware bit packing unit is to pack bits as coded according to the final macroblock coding decision into a data format.