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61 条记录 (耗时 0.071 秒)

    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory
    24.
    发明申请
    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
    包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存

    公开(公告)号：US20150186275A1

    公开(公告)日：2015-07-02

    申请号：US14142045

    申请日：2013-12-27

    申请人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    发明人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0888

    摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.

    摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理核心包括存储器控制器上方的多个缓存级别。 处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。 所述状态信息包括包含状态和不包含状态中的所选择的状态。 包含状态表示在内存中存在高速缓存行的副本或版本。 不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。 逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为 在包容性状态。

    CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS
    25.
    发明申请
    CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS 有权
    高速缓存设备和方法最小化存储器写回操作

    公开(公告)号：US20150178206A1

    公开(公告)日：2015-06-25

    申请号：US14136131

    申请日：2013-12-20

    申请人： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

    发明人： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0817 ,  G06F12/0815

    摘要： An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

    摘要翻译： 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

    Enhanced interconnect link width modulation for power savings
    28.
    发明授权
    Enhanced interconnect link width modulation for power savings 有权
    增强的互连链路宽度调制功率节省

    公开(公告)号：US08868955B2

    公开(公告)日：2014-10-21

    申请号：US13175794

    申请日：2011-07-01

    申请人： Venkatraman Iyer ,  Robert G. Blankenship ,  Dennis R. Halicki

    发明人： Venkatraman Iyer ,  Robert G. Blankenship ,  Dennis R. Halicki

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/171

    摘要： Methods and apparatus relating to enhanced interconnect link width modulation for power savings are described. In one embodiment, the width of a link is modified from a first width to a second width in response to a power management flit, while non-idle flits continue to be transmitted over the link after transmission of the power management flit. Other embodiments are also disclosed and claimed.

    摘要翻译： 描述了与增强的互连链路宽度调制相关的功率节省的方法和装置。 在一个实施例中，响应于电源管理飞行，链路的宽度从第一宽度修改为第二宽度，而在发送电源管理飞行之后，非空闲飞行继续在链路上传输。 还公开并要求保护其他实施例。

    Memory error detection and/or correction
    30.
    发明授权
    Memory error detection and/or correction 有权
    存储器错误检测和/或校正

    公开(公告)号：US08250435B2

    公开(公告)日：2012-08-21

    申请号：US12559953

    申请日：2009-09-15

    申请人： Robert G. Blankenship ,  Dennis W. Brzezinski ,  Edwin F. Mendez Valverde

    发明人： Robert G. Blankenship ,  Dennis W. Brzezinski ,  Edwin F. Mendez Valverde

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1004

    摘要： An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error.

    摘要翻译： 实施例可以包括可以检测和/或校正可包括数据字，循环冗余校验（CRC）字和奇偶校验字的数据码字中的至少一个错误的电路。 电路可以选择CRC字的一部分是否指示单个处理器是否已经访问了数据字。 数据字，CRC字和奇偶校验字可以在各自不同的存储器件组中可访问，每个不同的存储器件集合可以包括一个或多个相应的存储器件。 如果电路至少部分地基于数据码字和CRC字来检测CRC错误，并且该至少一个错误包括少于第一预定数量的错误，则电路可以确定在一个或多个相应的 存储器设备中的存储器设备设置至少一个错误，并且可以校正至少一个错误。