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公开(公告)号:US20120225529A1
公开(公告)日:2012-09-06
申请号:US13465551
申请日:2012-05-07
申请人: Chieh-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人: Chieh-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号: H01L21/336 , H01L21/425
CPC分类号: H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译: 本公开提供一种半导体器件,其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠,形成在栅极叠层的侧壁上的密封层,密封层具有内边缘和外边缘,内边缘与栅叠层的侧壁相接合 ,形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域,源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极(LDD)区域 密封层的边缘。
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公开(公告)号:US08159035B2
公开(公告)日:2012-04-17
申请号:US11840365
申请日:2007-08-17
申请人: Donald Y. Chao , Albert Chin , Ping-Fang Hung , Fong-Yu Yen , Kang-Cheng Lin , Kuo-Tai Huang
发明人: Donald Y. Chao , Albert Chin , Ping-Fang Hung , Fong-Yu Yen , Kang-Cheng Lin , Kuo-Tai Huang
CPC分类号: H01L21/28185 , H01L21/28097 , H01L21/28202 , H01L29/4975 , H01L29/517 , H01L29/665
摘要: A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.
摘要翻译: 半导体结构包括难熔金属硅化物层; 在难熔金属硅化物层上的富硅难熔金属硅化物层; 和富硅难熔金属硅化物层上的富金属难熔金属硅化物层。 难熔金属硅化物层,富硅难熔金属硅化物层和富含金属的难熔金属硅化物层包括相同的难熔金属。 半导体结构形成金属氧化物半导体器件的栅电极的一部分。
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公开(公告)号:US08105931B2
公开(公告)日:2012-01-31
申请号:US12424739
申请日:2009-04-16
申请人: Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
发明人: Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号: H01L21/3205 , H01L21/4763
CPC分类号: H01L27/092 , H01L21/823842 , H01L29/49 , H01L29/51
摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底,在半导体衬底上形成高k电介质层,在第一区域的高k电介质层上形成覆盖层,形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上,然后在第一区域中形成第一栅极堆叠,在第二区域中形成第二栅极叠层,保护第一栅极叠层中的第一金属层,同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺,以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。
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公开(公告)号:US20100052067A1
公开(公告)日:2010-03-04
申请号:US12424739
申请日:2009-04-16
申请人: Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
发明人: Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号: H01L27/092 , H01L21/8234
CPC分类号: H01L27/092 , H01L21/823842 , H01L29/49 , H01L29/51
摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底,在半导体衬底上形成高k电介质层,在第一区域的高k电介质层上形成覆盖层,形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上,然后在第一区域中形成第一栅极堆叠,在第二区域中形成第二栅极叠层,保护第一栅极叠层中的第一金属层,同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺,以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。
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公开(公告)号:US08836038B2
公开(公告)日:2014-09-16
申请号:US12883241
申请日:2010-09-16
申请人: Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人: Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号: H01L29/78 , H01L21/8238 , H01L21/28 , H01L29/66
CPC分类号: H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层,其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。
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公开(公告)号:US08450161B2
公开(公告)日:2013-05-28
申请号:US13465551
申请日:2012-05-07
申请人: Chien-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人: Chien-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
CPC分类号: H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译: 本公开提供一种半导体器件,其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠,形成在栅极叠层的侧壁上的密封层,密封层具有内边缘和外边缘,内边缘与栅叠层的侧壁相接合 ,形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域,源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极(LDD)区域 密封层的边缘。
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公开(公告)号:US20100052077A1
公开(公告)日:2010-03-04
申请号:US12422378
申请日:2009-04-13
申请人: Peng-Fu Hsu , Hsin-Chun Ko , Kang-Cheng Lin , Kuo-Tai Huang
发明人: Peng-Fu Hsu , Hsin-Chun Ko , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L21/28194 , H01L29/4966 , H01L29/513 , H01L29/517
摘要: A high-k metal gate structure including a buffer layer and method of fabrication of such, is provided. The buffer layer may interpose an interface oxide layer and a high-k gate dielectric layer. In one embodiment, the buffer layer includes aluminum oxide. The buffer layer and the high-k gate dielectric layer may be formed in-situ using an atomic layer deposition (ALD) process.
摘要翻译: 提供了包括缓冲层的高k金属栅极结构及其制造方法。 缓冲层可以插入界面氧化物层和高k栅介质层。 在一个实施例中,缓冲层包括氧化铝。 可以使用原子层沉积(ALD)工艺原位形成缓冲层和高k栅介质层。
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公开(公告)号:US20100044804A1
公开(公告)日:2010-02-25
申请号:US12427222
申请日:2009-04-21
申请人: Chien-Hao Chen , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang
发明人: Chien-Hao Chen , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang
CPC分类号: H01L21/28088 , H01L21/28194 , H01L21/28247 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.
摘要翻译: 本公开提供了一种半导体器件,其包括半导体衬底,形成在衬底中的晶体管,晶体管包括形成在衬底上的高k栅极电介质,高k栅极电介质具有从一个侧壁到 高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极,金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度,第二长度小于 第一长。
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公开(公告)号:US20100044803A1
公开(公告)日:2010-02-25
申请号:US12389535
申请日:2009-02-20
申请人: Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人: Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译: 本公开提供一种半导体器件,其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠,形成在栅极叠层的侧壁上的密封层,密封层具有内边缘和外边缘,内边缘与栅叠层的侧壁相接合 ,形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域,源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极(LDD)区域 密封层的边缘。
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公开(公告)号:US20090014813A1
公开(公告)日:2009-01-15
申请号:US11840365
申请日:2007-08-17
申请人: Donald Y. Chao , Albert Chin , Ping-Fang Hung , Foug-Yu Yen , Kang-Cheng Lin , Kuo-Tai Huang
发明人: Donald Y. Chao , Albert Chin , Ping-Fang Hung , Foug-Yu Yen , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号: H01L29/78
CPC分类号: H01L21/28185 , H01L21/28097 , H01L21/28202 , H01L29/4975 , H01L29/517 , H01L29/665
摘要: A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.
摘要翻译: 半导体结构包括难熔金属硅化物层; 在难熔金属硅化物层上的富硅难熔金属硅化物层; 和富硅难熔金属硅化物层上的富金属难熔金属硅化物层。 难熔金属硅化物层,富硅难熔金属硅化物层和富含金属的难熔金属硅化物层包括相同的难熔金属。 半导体结构形成金属氧化物半导体器件的栅电极的一部分。
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