公开(公告)号：US06285068B1

公开(公告)日：2001-09-04

申请号：US09053627

申请日：1998-04-02

Applicant: Dong-Man Kang ,  Jung-Ho Kang

Inventor： Dong-Man Kang ,  Jung-Ho Kang

IPC: H01L2900

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides antifuses that enhance the efficiency of a field programmable gate array and that decrease chip size. The antifuses comprise a plurality of first conductive layers formed on a substrate, an antifuse layer formed on a plurality of the first conductive layers, and a second conductive layer formed on the antifuse layer. A method of fabricating the antifuses comprises the steps of forming a plurality of first conductive layers on predetermined portions of a substrate, forming an insulating layer over the surface of the substrate, selectively etching the insulating layer to form a via hole that is connected with a plurality of the first conductive layers, forming an antifuse layer on a predetermined portion of the insulating layer, including the via hole, and forming a second conductive layer on a predetermined portion of the insulating layer, including the antifuse layer.

Abstract translation: 本发明提供了提高现场可编程门阵列效率并降低芯片尺寸的反熔丝。 反熔丝包括形成在基板上的多个第一导电层，形成在多个第一导电层上的反熔丝层，以及形成在反熔丝层上的第二导电层。 制造抗熔丝的方法包括以下步骤：在衬底的预定部分上形成多个第一导电层，在衬底的表面上形成绝缘层，选择性地蚀刻绝缘层以形成通孔，其与 多个第一导电层，在包括通孔的绝缘层的预定部分上形成反熔丝层，并在包括反熔丝的绝缘层的预定部分上形成第二导电层。