公开(公告)号：US09628655B2

公开(公告)日：2017-04-18

申请号：US15141341

申请日：2016-04-28

Applicant: KYOCERA Document Solutions Inc.

Inventor： Katsuo Mikashima

IPC: G06F15/00 ,  H04N1/00

CPC classification number: H04N1/00899

Abstract: An image forming apparatus includes a main CPU, a sub CPU, a mode control circuit, a voltage monitoring circuit, a reset circuit, and a prevention circuit. The voltage monitoring circuit outputs a first abnormality detection signal if the operating voltage supplied to the main CPU is determined as abnormal. The voltage monitoring circuit outputs a second abnormality detection signal if the operating voltage supplied to the sub CPU is determined as abnormal. The reset circuit resets the main CPU and the sub CPU if at least one of the first abnormality detection signal and the second abnormality detection signal is transmitted. The prevention circuit prevents the transmission of the first abnormality detection signal to the reset circuit in the second mode.