公开(公告)号：US5628025A

公开(公告)日：1997-05-06

申请号：US483778

申请日：1995-06-07

申请人： Moo-Taek Chung ,  Jim Childers ,  Hiroshi Miyaguchi ,  Manfred Becker

发明人： Moo-Taek Chung ,  Jim Childers ,  Hiroshi Miyaguchi ,  Manfred Becker

IPC分类号： F02B75/02 ,  G06F15/80 ,  H04N5/14 ,  H04N5/775 ,  H04N9/64 ,  H04N9/79 ,  G06F3/14

CPC分类号： G06F15/8092 ,  H04N5/775 ,  F02B2075/027 ,  H04N5/14 ,  H04N9/641 ,  H04N9/79

摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

摘要翻译： 一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。 该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。

公开(公告)号：US5452425A

公开(公告)日：1995-09-19

申请号：US163606

申请日：1993-12-07

申请人： Jim Childers ,  Hiroshi Miyaguchi ,  Peter Reinecke

发明人： Jim Childers ,  Hiroshi Miyaguchi ,  Peter Reinecke

IPC分类号： F02B75/02 ,  G06F15/80 ,  G06F9/26 ,  G06F9/06

CPC分类号： G06F15/8092 ,  F02B2075/027

摘要： A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.

摘要翻译： 描述了在同步向量处理器中提供数字常数序列的常数发生器。 常数发生器包括用于存储组织成多个数据常数模式和循环位结束的数据字的恒定循环存储器，用于向恒定循环存储器提供顺序地址的常数循环计数器和用于加载 计数器与存储在恒定循环存储器中的期望常数模式相关联的一组预定起始地址中的一个。 另外，公开了一种在所述常数发生器中提供数字常数序列的方法，包括以多个恒定模式存储多个数据字的步骤，其中每个常数模式包括循环位结束，向 恒定循环存储器，并向恒定循环存储器提供顺序地址。

公开(公告)号：US5327541A

公开(公告)日：1994-07-05

申请号：US887228

申请日：1992-05-18

申请人： Peter Reinecke ,  Jimmie D. Childers ,  Hiroshi Miyaguchi ,  Moo-Taek Chung

发明人： Peter Reinecke ,  Jimmie D. Childers ,  Hiroshi Miyaguchi ,  Moo-Taek Chung

IPC分类号： F02B75/02 ,  G06F15/80 ,  G06F12/00 ,  G06F15/76

CPC分类号： G06F15/8092 ,  G06F15/8015 ,  F02B2075/027

摘要： An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector. The comparator compares the relative address with the output of the modulus register, determining whether selected ones of the addressed register file locations fall inside or outside of the rotation area, and send an appropriate signal to the logic circuitry, an OR gate. This OR gate also receives a rotate or not-rotate signal. Consequently, either an absolute address equal to (the value of the relative address-2 * the offset value) mod (8 * the value in the modulus register) or equal to the relative address, based on predetermined conditions, is utilized to access rotationally data from the register file.

摘要翻译： 一种用于在寄存器文件存储器中执行数据旋转的装置和方法。 该装置使用包括旋转值，模数和偏移寄存器的旋转地址生成器，比较器，数据选择器，逻辑电路和减法器。 由指令程序存储器指定寄存器文件存储器的预定区域（PxQ）和与旋转区域中要旋转的位数相对应的旋转值。 指令译码器向数据的即将转动的寄存器文件，模数寄存器，旋转值寄存器和偏移寄存器发出信号，从而可以加载模数和旋转值寄存器以及复位偏移寄存器。 计数器提供比较器和数据选择器的相对地址。 比较器将相对地址与模数寄存器的输出进行比较，确定所寻址的寄存器文件位置中选定的位置是否位于旋转区域的内部或外部，并向OR逻辑电路发送适当的信号。 该或门也接收旋转或非旋转信号。 因此，利用等于（相对地址-2 *偏移值的值）mod（8 *模数寄存器中的值）或等于相对地址的绝对地址（基于预定条件）被旋转地访问 来自寄存器文件的数据。

公开(公告)号：US5093722A

公开(公告)日：1992-03-03

申请号：US486662

申请日：1990-03-01

申请人： Hiroshi Miyaguchi ,  Jimmie D. Childers

发明人： Hiroshi Miyaguchi ,  Jimmie D. Childers

IPC分类号： H04N5/14 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N5/46 ,  H04N7/01 ,  H04N7/015 ,  H04N9/64 ,  H04N9/77 ,  H04N9/78 ,  H04N11/04 ,  H04N11/20

CPC分类号： H04N5/4448 ,  H04N5/144 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N7/012 ,  H04N9/646 ,  H04N9/78

摘要： A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system.

公开(公告)号：US5091783A

公开(公告)日：1992-02-25

申请号：US486663

申请日：1990-03-01

申请人： Hiroshi Miyaguchi

发明人： Hiroshi Miyaguchi

IPC分类号： H04N5/14 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N9/64 ,  H04N9/78

CPC分类号： H04N5/4448 ,  H04N5/144 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N7/012 ,  H04N9/646 ,  H04N9/78

摘要： A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suitable for television processing. The processor receives data samples fo each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a still picture may be displayed.

摘要翻译： 电视接收系统包括具有至少一个单指令多数据处理器的数字单元，特别适用于电视处理。 处理器连续地接收每个水平行字的数据样本，但并行处理该行。 处理器具有并发操作的输入，计算和输出层。 内部寄存器文件模拟行存储器，以消除对外部线路存储器的需要。 处理器可以用从主机开发系统下载到其中的各种改进的定义电视任务进行编程。 场存储器和多路复用器控制数据流，从而可以显示静止图像。

公开(公告)号：US4510578A

公开(公告)日：1985-04-09

申请号：US352236

申请日：1982-02-25

申请人： Hiroshi Miyaguchi ,  Hisaharu Takeuchi

发明人： Hiroshi Miyaguchi ,  Hisaharu Takeuchi

IPC分类号： G06F7/548 ,  G06F17/16 ,  H04N11/04 ,  G06F15/332

CPC分类号： H04N11/044

摘要： The invention provides an encoder for subjecting an input signal to the orthogonal transform for band compression and encoding. The encoder has a sample and hold circuit which samples the input signal at a sampling frequency three times that of the input signal, and an orthogonal transform unit which subjects the sampled signal to the orthogonal transform using as a coefficient an orthogonal matrix function of the order of 3n (where n is an integer of 2 or more) having as a minor matrix an orthogonal matrix of the order of 3: ##EQU1## having given numbers a, b and c as matrix elements. By maintaining the sampling frequency low, the frequency components of the input signal may be concentrated in a small number of transform outputs without causing an increase in the amount of data to be processed, without using a multiplier and without requiring an increase in the processing speed. The input signal is thus effectively band compressed and encoded.

摘要翻译： 本发明提供一种用于对输入信号进行正交变换以进行频带压缩和编码的编码器。 编码器具有采样保持电路，其采样频率为输入信号三倍的采样频率，以及正交变换单元，其使采样信号进行正交变换，作为系数的顺序正交矩阵函数 具有作为次要矩阵的3n（其中n是2或更大的整数）具有给定数量a，b和c作为矩阵元素的3：3的正交矩阵。 通过保持采样频率较低，输入信号的频率分量可以集中在少量的变换输出中，而不会导致要处理的数据量的增加，而不需要使用乘法器，而不需要增加处理速度 。 因此，输入信号被有效地进行频带压缩和编码。