-
公开(公告)号：US5926559A
公开(公告)日：1999-07-20
申请号：US844601
申请日：1997-04-21
申请人： Kenichi Ohta
发明人： Kenichi Ohta
CPC分类号： G06T11/001
摘要： A select-signal generator generates a select signal according to a magnitude comparison between the low-order bit data R.sub.l, G.sub.l, and B.sub.l of input R, G, and B color signals. A table memory generates three addresses with the use of the high-order bit data R.sub.u, G.sub.u, and B.sub.u according to the select signal and outputs lattice point data C11, C12, and C13 corresponding to the three addresses. Another table memory outputs one lattice data C2 for a lattice point which is offset from lattice points in the above-described table memory by addressing with the use of the high-order bit data. Then, an interpolation circuit executes interpolation according to the data C11, C12, C13, and C2 at four lattice points which form a triangular pyramid as a minimum interpolation space.
摘要翻译： 选择信号发生器根据输入R，G和B颜色信号的低位数据R1，G1和B1之间的幅度比较产生选择信号。 表存储器根据选择信号使用高阶位数据Ru，Gu和Bu产生三个地址，并输出与三个地址对应的格点数据C11，C12和C13。 另一个表存储器通过使用高阶位数据进行寻址而输出一个格数据C2，用于从上述表存储器中的格点偏移的格点。 然后，内插电路根据构成三角锥的4个格点的数据C11，C12，C13，C2进行插值，作为最小内插空间。
-
公开(公告)号：US5768410A
公开(公告)日：1998-06-16
申请号：US854725
申请日：1997-05-12
申请人： Kenichi Ohta , Takashi Yabe
发明人： Kenichi Ohta , Takashi Yabe
CPC分类号： H04N1/6016
摘要： A color signal processing apparatus which is capable of providing satisfactory operation accuracy while keeping the memory size relatively small. A dividing circuit divides three input signals R, G, and B into upper bit data and lower bit data. A first table memory stores output values for all combinations of the three upper bit signals, the upper bit data of the three input signals being accepted as address signals and a first output value being provided. A second table memory stores the output values for all combinations of signal values obtained by adding a prescribed offset (e.g. 2.sup.NL /2) to a signal value which is expressed by upper bits, upper bit data of the three input signals being accepted as address signals and a second output value being provided. An interpolation circuit outputs a final output signal in accordance with the output value of the first table memory, the output value of the second table memory and the lower bit data.
摘要翻译： 一种能够在保持存储器尺寸相对较小的同时提供令人满意的操作精度的彩色信号处理装置。 分频电路将三个输入信号R，G和B分为高位数据和低位数据。 第一表存储器存储三个高位位信号的所有组合的输出值，三个输入信号的高位数据被接受为地址信号，并且提供第一输出值。 第二表存储器存储通过将规定的偏移（例如2NL / 2）加上由高位表示的信号值而获得的信号值的所有组合的输出值，三个输入信号的高位数据被接受为地址信号 并提供第二输出值。 内插电路根据第一表存储器的输出值，第二表存储器的输出值和低位数据输出最终输出信号。
-
公开(公告)号：US5130819A
公开(公告)日：1992-07-14
申请号：US598157
申请日：1990-10-16
申请人： Kenichi Ohta
发明人： Kenichi Ohta
CPC分类号： H04N1/4053
摘要： An image processing apparatus that converts multi-level pixel data to binary pixel data and outputs it includes, in one embodiment, an input device for accepting multi-level pixel data, a binary conversion device for converting multi-level pixel data input from the input device to binary pixel data on the basis of a threshold value, an output device for outputting the binary pixel data which has been binarized by the binary conversion device, a first and a second memory in which errors and binary pixel data are stored, respectively, a correction device for correcting multi-level pixel data, a first and a second average density computation device for computing an average density value, a computation device for computing the average value of the average density values computed by the first and second average density computation devices as a threshold value, a detection device for detecting an error value, and a distribution device for distributing an error value to unbinarized pixel positions.
摘要翻译： 将多级像素数据转换为二进制像素数据并输出的图像处理装置在一个实施例中包括用于接受多级像素数据的输入装置，用于转换从输入端输入的多级像素数据的二进制转换装置 基于阈值设备到二进制像素数据;输出装置，用于输出由二进制转换装置二进制化的二进制像素数据;分别存储错误和二进制像素数据的第一和第二存储器; 用于校正多级像素数据的校正装置，用于计算平均浓度值的第一和第二平均浓度计算装置，用于计算由第一和第二平均浓度计算装置计算的平均密度值的平均值的计算装置 作为阈值，用于检测误差值的检测装置，以及用于将误差值分配给非单元化像素posi的分配装置 。
-
-
搜索结果
23 条记录 (耗时 0.016 秒)
