公开(公告)号：US20080071512A1

公开(公告)日：2008-03-20

申请号：US11942309

申请日：2007-11-19

申请人： Ioana Graur ,  Kafai Lai ,  Rama Singh

发明人： Ioana Graur ,  Kafai Lai ,  Rama Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。

公开(公告)号：US07266798B2

公开(公告)日：2007-09-04

申请号：US11163264

申请日：2005-10-12

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Azalia Krasnoperova ,  Ioana Graur

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Azalia Krasnoperova ,  Ioana Graur

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.

摘要翻译： 通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。 该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束 特征对其他层的影响。 该方法可以在用于在计算机系统上执行的计算机程序产品中实现。 所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

公开(公告)号：US07175942B2

公开(公告)日：2007-02-13

申请号：US10708055

申请日：2004-02-05

申请人： Lars W. Liebmann ,  Ioana Graur

发明人： Lars W. Liebmann ,  Ioana Graur

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G03F1/30

摘要： A method of designing a layout of an alternating phase shifting mask for projecting an image of an integrated circuit design having a plurality of features to be projected using alternating phase shifting segments, including a gate-shrink region of a transistor having a critical width along a length thereof that extends beyond a diffusion region. The method also provides alternating phase shift design rules based on alternating phase shift design parameters comprising minimum phase width, minimum phase-to-phase spacing, and minimum extension of critical width beyond another feature. The method then includes identifying portions of the integrated circuit layout having a critical width feature that violate the alternating phase shift design rules, and reducing the length that the critical width gate-shrink region feature extends beyond the other diffusion region feature to the minimum extension. An alternating phase shifting mask layout is then generated in conformance with the alternating phase shift design rules.

摘要翻译： 一种设计交替相移掩模的布局的方法，用于使用交变相移段来投影具有要投影的多个特征的集成电路设计的图像，所述交变相移段包括沿着沿着具有临界宽度的晶体管的栅极收缩区域 其长度延伸超过扩散区域。 该方法还提供基于交替相移设计参数的交替相移设计规则，其包括最小相位宽度，最小相间间隔以及临界宽度超出另一特征的最小延伸。 该方法然后包括识别具有违反交替相移设计规则的临界宽度特征的集成电路布局的部分，并且减小临界宽度栅 - 收缩区域特征延伸超出另一扩散区域特征到最小延伸的长度。 然后根据交变相移设计规则生成交替的相移掩模布局。

公开(公告)号：US06901576B2

公开(公告)日：2005-05-31

申请号：US10300240

申请日：2002-11-20

申请人： Lars W. Liebmann ,  Carlos A. Fonseca ,  Ioana Graur

发明人： Lars W. Liebmann ,  Carlos A. Fonseca ,  Ioana Graur

IPC分类号： G03C5/00 ,  G03F1/30 ,  G03F9/00 ,  G06F9/40 ,  G06F17/50

CPC分类号： G03F1/30

摘要： A method is provided for designing an altPSM mask including a substrate. The method includes the following steps. Provide a circuit layout. Identify critical elements of the circuit layout. Provide a cutoff layout dimension. Identify critical segments of the circuit layout which are critical elements with a sub-cutoff dimension less than the cutoff dimension. Create basic phase shapes associated with the critical segments. Remove layout violations from the phase shapes. Determine whether the widths of phase shapes associated with a critical segment have unequal narrower and wider widths. If YES, then widen each narrower phase shape to match the width of wider phase shape associated with the critical segment and repeat the steps starting with removal of layout violations until the test answer is NO. When the test answer is NO, provide a layout pattern to an output.

摘要翻译： 提供了一种用于设计包括衬底的altPSM掩模的方法。 该方法包括以下步骤。 提供电路布局。 识别电路布局的关键要素。 提供截止布局维度。 识别电路布局的关键部分，这些部分是具有小于截止尺寸的子切割尺寸的关键元件。 创建与关键段相关联的基本相位形状。 从相位形状中删除布局违例。 确定与临界段相关联的相位形状的宽度是否具有不相等的较窄和较宽的宽度。 如果是，则扩大每个较窄的相位形状以匹配与关键段相关联的较宽相位形状的宽度，并重复从删除布局违规开始的步骤，直到测试答案为否。 当测试答案为NO时，向输出提供布局模式。

公开(公告)号：US06609245B2

公开(公告)日：2003-08-19

申请号：US09997657

申请日：2001-11-29

申请人： Lars W. Liebmann ,  Carlos A. Fonseca ,  Ioana Graur ,  Young O. Kim

发明人： Lars W. Liebmann ,  Carlos A. Fonseca ,  Ioana Graur ,  Young O. Kim

IPC分类号： G06F1750

CPC分类号： G03F1/30

摘要： A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

摘要翻译： 描述了一种方法和计算机程序产品，用于优化根据规则层级将二进制属性分配给设计元素的电路布局的设计。 例如，交替相移掩模（altPSM）的设计首先根据规定分配相位形状的规则进行优化，该相位形状使关键电路元件的图像质量最大化，然后进一步优化以最小化掩模可制造性问题，而不会显着增加设计的复杂性 工艺流程。 根据附加规则进一步优化设计可以按顺序降低的优先顺序执行。 由于规则的优先级减少，只要优先级较高的规则不被侵犯，某些违反较低优先权规则就可以接受。

公开(公告)号：US09087739B2

公开(公告)日：2015-07-21

申请号：US12581422

申请日：2009-10-19

申请人： Derren N. Dunn ,  Ioana Graur ,  Scott M. Mansfield

发明人： Derren N. Dunn ,  Ioana Graur ,  Scott M. Mansfield

IPC分类号： G06F17/50 ,  H01L21/66 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L22/12 ,  G03F1/36 ,  G03F1/80 ,  G03F7/70441 ,  G03F7/705 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816

摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

摘要翻译： 通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度 由于微加载和RIE滞后（包括反​​RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案 这将在整个过程完成时产生期望的特征尺寸和形状。 可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。

公开(公告)号：US08108804B2

公开(公告)日：2012-01-31

申请号：US12355814

申请日：2009-01-19

申请人： Ioana Graur ,  Scott M. Mansfield

发明人： Ioana Graur ,  Scott M. Mansfield

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the window area; selecting a solution, from a library of pre-computed solutions, based on a category of the window area; and applying the solution to the hot spot. A service-oriented architecture (SOA) system that synchronizes the design to the process is also provided.

摘要翻译： 本发明的实施例提供一种执行光掩模校正的方法。 该方法包括识别违反一个或多个预定义规则的照相掩模中的热点; 在围绕热点的照相掩模中创建一个窗口区域; 分类窗口区域; 基于窗口区域的类别从预先计算的解决方案库中选择解决方案; 并将解决方案应用于热点。 还提供了将设计与流程同步的面向服务架构（SOA）系统。

公开(公告)号：US08078995B2

公开(公告)日：2011-12-13

申请号：US12349104

申请日：2009-01-06

申请人： Jaione Tirapu Azpiroz ,  Alan E. Rosenbluth ,  Ioana Graur

发明人： Jaione Tirapu Azpiroz ,  Alan E. Rosenbluth ,  Ioana Graur

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/705

摘要： Modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography, is provided. An isofield perturbation to a thin mask representation of the mask is provided by determining, for the components of the illumination, differences between the electric field on a feature edge having finite thickness and on the corresponding feature edge of a thin mask representation. An isofield perturbation is obtained from a weighted coherent combination of the differences for each illumination polarization. The electric field of a mask having topographic edges is represented by combining a thin mask representation with the isofield perturbation applied to each edge of the mask.

摘要翻译： 提供了用于制造半导体集成电路的光掩模设计中使用的光刻工艺的建模，特别是对由于照明光与掩模形貌的相互作用而引起的复杂影响的建模。 通过对于照明的组件，确定具有有限厚度的特征边缘上的电场与薄掩模表示的相应特征边缘之间的差异来提供对掩模的薄掩模表示的异场扰动。 从每个照明偏振的差的加权相干组合获得异场扰动。 通过将薄掩模表示与应用于掩模的每个边缘的异场扰动组合来表示具有形貌边缘的掩模的电场。

公开(公告)号：US08059884B2

公开(公告)日：2011-11-15

申请号：US11937073

申请日：2007-11-08

申请人： Maharaj Mukherjee ,  Ioana Graur ,  Alan E. Rosenbluth

发明人： Maharaj Mukherjee ,  Ioana Graur ,  Alan E. Rosenbluth

IPC分类号： G06K9/20

CPC分类号： G06K9/036 ,  G03F7/70441

摘要： Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of process parameters to said one or more tight clusters; and reporting an error when at least one of said process parameters is away from said one or more tight clusters.

摘要翻译： 本发明的实施例提供了一种执行掩模布局的可印刷性验证的方法。 该方法包括创建一个或多个紧密簇; 计算与所述掩模上的点相关联的一组过程参数; 将所述一组过程参数与所述一个或多个紧密簇进行比较; 并且当至少一个所述过程参数远离所述一个或多个紧密簇时报告错误。

公开(公告)号：US20110091815A1

公开(公告)日：2011-04-21

申请号：US12581422

申请日：2009-10-19

申请人： Derren N. Dunn ,  Ioana Graur ,  Scott M. Mansfield

发明人： Derren N. Dunn ,  Ioana Graur ,  Scott M. Mansfield

IPC分类号： G03F7/20

CPC分类号： H01L22/12 ,  G03F1/36 ,  G03F1/80 ,  G03F7/70441 ,  G03F7/705 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816

摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

摘要翻译： 通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度 由于微加载和RIE滞后（包括反​​RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案 这将在整个过程完成时产生期望的特征尺寸和形状。 可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。