公开(公告)号：US5773854A

公开(公告)日：1998-06-30

申请号：US892827

申请日：1997-07-15

申请人： Nicholas F. Pasch

发明人： Nicholas F. Pasch

IPC分类号： H01L27/118 ,  H01L27/10

CPC分类号： H01L27/11898 ,  Y10S148/028

摘要： A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

摘要翻译： 半导体器件包括具有与输入/输出（I / O）电路器件阵列电连接的逻辑门阵列的结构，并且还与可与该半导体器件进行电连接的连接器焊盘阵列电连接 。 逻辑门阵列是线性连续的，并且沿着至少第一轴线到达施加半导体晶片的边缘的边界是无界的。 I / O电路器件和连接器焊盘的阵列被布置成与逻辑门阵列相邻，并且在一个实施例中是平行的。 通过从逻辑门阵列的条状部分切割所选择的长度，可以容易地提供包括定制数量的单个逻辑门元件的集成电路结构。 所需的连接器焊盘和I / O电路特性由相邻的I / O电路器件阵列和相邻阵列的连接器焊盘提供。

公开(公告)号：US5769692A

公开(公告)日：1998-06-23

申请号：US772310

申请日：1996-12-23

申请人： Nicholas F. Pasch ,  David J. Heine ,  Jayashree Kalpathy Cramer

发明人： Nicholas F. Pasch ,  David J. Heine ,  Jayashree Kalpathy Cramer

IPC分类号： B24B37/30 ,  H01L21/306 ,  B24B13/02

CPC分类号： B24B37/30

摘要： A substrate holder assembly for immobilizing an integrated circuit (IC) wafer during polishing is described. The substrate holder includes a base plate sized to support the integrated circuit (IC) wafer, a circumferential restraint member arranged with respect to the base plate to engage the IC wafer's edges and a carrier assembly disposed above the base plate and below the IC wafer. The carrier assembly includes a film having a surface that is characterized by a substantially oblate spheroid or hyperboloid surface of rotation, wherein the surface of the film is capable of supporting the IC wafer in a manner causing the IC wafer to bow according to the surface of rotation.

摘要翻译： 描述了用于在抛光期间固定集成电路（IC）晶片的衬底保持器组件。 衬底保持器包括尺寸适于支撑集成电路（IC）晶片的基板，相对于基板布置以接合IC晶片边缘的周向约束部件和设置在基板上方和IC晶片下方的载体组件。 载体组件包括具有表面的膜，其特征在于基本上为扁圆球形或双曲面的旋转表面，其中膜的表面能够以使IC晶片根据 回转。

公开(公告)号：US5739584A

公开(公告)日：1998-04-14

申请号：US485060

申请日：1995-06-07

申请人： Nicholas F. Pasch

发明人： Nicholas F. Pasch

IPC分类号： H01L21/50 ,  H01L23/057 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

CPC分类号： H01L23/5382 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195

摘要： A modular multi-pin package for an integrated circuit die is formed of simple standardized parts and a readily redesigned, integrated circuit specific circuit substrate possessing a design pattern for providing electrical connection between die pads and output pins. The substrate includes a pattern of electrically conductive traces each terminating in a die pattern at an interior portion of the substrate and terminating in a pattern of pin connecting pads at a peripheral portion of the substrate. A pin holding frame is formed with a plurality of holes in which are inserted a selected number and pattern of package terminal pins, each having a shank protruding outwardly from the pin holder for connection to external circuits or components and each having an inner head pressed against one of the pin connecting pads of the substrate circuit traces. A conductive epoxy may be interposed between the pin heads and the substrate pin connecting pads to ensure good electrical contact, and a dielectric gas impermeable adhesive may be employed to secure the pin holder frame to the substrate. A die is inserted through a central aperture of the pin holder frame for attachment to the substrate by connecting the die pads to the die connecting ends of the substrate circuit. The package is completed by bonding a gas impermeable lid of metal or a transparent material to the pin holder frame to cover the opening of the frame and seal the die within the package.

摘要翻译： 用于集成电路管芯的模块化多引脚封装由简单的标准化部件和易于重新设计的集成电路专用电路基板形成，该电路基板具有用于在管芯焊盘和输出引脚之间提供电连接的设计图案。 衬底包括导电迹线图案，每个导体迹线终止于衬底的内部处的管芯图案，并终止于衬底的周边部分处的引脚连接焊盘的图案。 销保持框架形成有多个孔，其中插入有选定数量和包装端子销的图案，每个具有从销保持器向外突出的柄，用于连接到外部电路或部件，并且每个具有压靠 衬底电路迹线的引脚连接焊盘之一。 可以在引脚头和衬底引脚连接焊盘之间插入导电环氧树脂以确保良好的电接触，并且可以采用电介质气体不可渗透的粘合剂来将销保持器框架固定到衬底。 通过将管芯焊盘连接到衬底电路的管芯连接端，将管芯插入穿过销保持器框架的中心孔以附接到衬底。 通过将金属或透明材料的气体不可渗透的盖接合到销保持器框架以覆盖框架的开口并将模具密封在包装中来完成包装。

公开(公告)号：US5689134A

公开(公告)日：1997-11-18

申请号：US685772

申请日：1996-07-24

申请人： Nicholas F. Pasch ,  Aldona M. Butkus

发明人： Nicholas F. Pasch ,  Aldona M. Butkus

IPC分类号： H01L23/552 ,  H01L23/522

CPC分类号： H01L23/552 ,  H01L2924/0002

摘要： An integrated circuit structure is described having a non-metallic electrically conductive plate preferably placed over an insulating layer formed over the uppermost layer of metal lines. The electrically conductive non-metallic plate is operative to terminate electric field lines emanating from at least some of the metal lines in the metal layers under the insulating layer beneath the non-metallic electrically conductive plate, particularly the uppermost metal lines, i.e., those spaced the farthest distance from the underlying semiconductor substrate. The conductive plate may be connected to either a ground line or a power line. In another embodiment, the non-metallic electrically conductive plate may be located between at least the uppermost layer of metal lines and one or more lower layers of metal lines, with insulating layers separating the non-metallic electrically conductive plate from such metal lines.

摘要翻译： 描述了一种集成电路结构，其具有优选放置在形成在金属线的最上层上的绝缘层上的非金属导电板。 导电非金属板可操作以终止从非金属导电板下面的绝缘层下面的金属层中的至少一些金属线发出的电场线，特别是最上面的金属线，即间隔开的那些 距离底层半导体衬底最远的距离。 导电板可以连接到地线或电源线。 在另一个实施例中，非金属导电板可以位于至少金属线的最上层和一个或多个下层金属线之间，绝缘层将非金属导电板与这些金属线分开。

公开(公告)号：US5659189A

公开(公告)日：1997-08-19

申请号：US473543

申请日：1995-06-07

申请人： Nicholas F. Pasch

发明人： Nicholas F. Pasch

IPC分类号： H01L27/118 ,  H01L27/10

CPC分类号： H01L27/11898 ,  Y10S148/028

摘要： A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

摘要翻译： 半导体器件包括具有与输入/输出（I / O）电路器件阵列电连接的逻辑门阵列的结构，并且还与可与该半导体器件进行电连接的连接器焊盘阵列电连接 。 逻辑门阵列是线性连续的，并且沿着至少第一轴线到达施加半导体晶片的边缘的边界是无界的。 I / O电路器件和连接器焊盘的阵列被布置成与逻辑门阵列相邻，并且在一个实施例中是平行的。 通过从逻辑门阵列的条状部分切割所选择的长度，可以容易地提供包括定制数量的单个逻辑门元件的集成电路结构。 所需的连接器焊盘和I / O电路特性由相邻的I / O电路器件阵列和相邻阵列的连接器焊盘提供。

公开(公告)号：US5554484A

公开(公告)日：1996-09-10

申请号：US359046

申请日：1994-12-19

申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

IPC分类号： G02B17/00 ,  G02B26/02 ,  G02B27/09 ,  G02F1/19 ,  G02F1/33 ,  G03F7/20 ,  G21K1/04 ,  G03F7/004

CPC分类号： G02B27/0994 ,  G02B17/00 ,  G02B26/02 ,  G02F1/19 ,  G03F7/70008 ,  G03F7/702 ,  G03F7/70375 ,  G21K1/04 ,  G02F1/33 ,  Y10S430/107 ,  Y10S430/108

摘要： Fine, sub-micron line features and patterns are created in a radiation sensitive resist layer on a semiconductor wafer by a beam of short wavelength gamma rays. The resist layer includes photoresist which is substantially chemically inactive in response to the gamma rays. The photoresist is either doped or covered with a material that absorbs gamma rays and in response emits secondary radiation of a different wavelength, preferably photons, that is actinic with respect to the photoresist. The resist layer enables using radiation sources having better resolving ability than conventional photolithographic sources to perform near-field and direct-write lithography.

摘要翻译： 通过短波长γ射线束在半导体晶片上的辐射敏感抗蚀剂层中产生细的亚微米线特征和图案。 抗蚀剂层包括响应于γ射线基本上化学惰性的光致抗蚀剂。 光致抗蚀剂被掺杂或被吸收伽马射线的材料覆盖，并且响应于发射相对于光致抗蚀剂而光化的不同波长的次级辐射，优选光子。 抗蚀剂层能够使用具有比常规光刻源更好的分辨能力的辐射源来进行近场和直写光刻。

公开(公告)号：US5489804A

公开(公告)日：1996-02-06

申请号：US106157

申请日：1993-08-12

申请人： Nicholas F. Pasch

发明人： Nicholas F. Pasch

IPC分类号： G03F7/20 ,  H01L21/56 ,  H01L21/60 ,  H01L31/0232 ,  H05K3/30 ,  H05K3/34 ,  H01L39/02

CPC分类号： G03F7/70433 ,  H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L31/0232 ,  H05K3/3436 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K2201/10424 ,  H05K2203/167 ,  H05K3/303 ,  H05K3/3431 ,  H05K3/3489 ,  Y02P70/613 ,  Y10T29/49144

摘要： A ring-shaped, substantially planar structure is described for interposing between a chip and a substrate. The ring-shaped structure, being more flexible than a similar solid structure, conforms more readily to any irregularities in the surface of the substrate. Through holes in the planar structure facilitate controlled formation of reflow solder connections between the chip and the substrate. In one embodiment, the ring shape of the planar structure has a gap to facilitate better conformance to irregularities in the surface of the substrate and to minimize "levering" of the chip. Other embodiments provide for "kerfing" of the ring-shaped planar structure to permit even greater flexibility of the structure and less levering of the chip. Angled through holes permit adaptation of mismatched solder bump patterns on the chip and substrate. Other embodiments are directed to conductive elements embedded within the planar structure for making electrical contact with selected solder joints and/or to prevent electrogalvanic corrosion of solder bumps with different compositions.

摘要翻译： 描述了用于插入芯片和基板之间的环形基本上平面的结构。 比类似的固体结构更柔软的环形结构更容易地符合衬底表面中的任何不规则性。 平面结构中的通孔有助于在芯片和衬底之间控制形成回焊焊接连接。 在一个实施例中，平面结构的环形具有间隙以便于更好地符合衬底的表面中的不规则性并且最小化芯片的“杠杆”。 其他实施例提供了环形平面结构的“切割”，以允许结构的更大的灵活性和更小的芯片的杠杆作用。 通过孔的角度允许调整芯片和衬底上不匹配的焊料凸块图案。 其他实施例涉及嵌入在平面结构内的导电元件，用于与所选择的焊点形成电接触和/或防止具有不同组成的焊料凸块的电镀锌腐蚀。

公开(公告)号：US5478698A

公开(公告)日：1995-12-26

申请号：US105261

申请日：1993-08-12

申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

IPC分类号： H01J37/317 ,  G03F7/20 ,  H01J37/30

CPC分类号： B82Y15/00 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/06341 ,  H01J2237/31735 ,  Y10S430/143 ,  Y10S977/855

摘要： A technique is describe for effecting very-high resolution semiconductor lithography using direct-write afocal electron-beam exposure of a sensitized wafer. A positioning mechanism and needle-like probe similar to those used in scanning-tunneling microscopy are used in conjunction with a controllable electron field emission source to produce a near-field electron beam capable of exposing an electron-beam sensitive resist on a wafer surface. Conventional e-beam resists are used. The technique can be used in conjunction with scanning-tunneling-like operation of the apparatus to record the appearance and nature of the wafer surface, thereby providing information about the location of underlying features. This location information can be used to assist in aligning the exposure patterns to existing structures in the semiconductor wafer. A multi-probe embodiment with separately controllable field emission sources provides for improved productivity by permitting contemporaneous exposure of multiple sites on a single wafer.

摘要翻译： 描述了一种技术，用于使用致敏晶片的直接写入无电子束曝光来实现非常高分辨率的半导体光刻。 与扫描隧道显微镜中使用的类似的定位机构和针状探针与可控电子场发射源结合使用以产生能够在晶片表面上暴露电子束敏感抗蚀剂的近场电子束。 使用常规电子束抗蚀剂。 该技术可以与装置的扫描隧道式操作一起使用，以记录晶片表面的外观和性质，从而提供关于底层特征的位置的信息。 该位置信息可用于帮助将曝光图案对准半导体晶片中的现有结构。 具有单独可控的场致发射源的多探针实施例通过允许在单个晶片上同时曝光多个位置来提供提高的生产率。

公开(公告)号：US5477086A

公开(公告)日：1995-12-19

申请号：US55429

申请日：1993-04-30

申请人： Michael D. Rostoker ,  Nicholas F. Pasch

发明人： Michael D. Rostoker ,  Nicholas F. Pasch

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L24/12 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/4007 ,  H01L2221/68313 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/09745 ,  H05K2201/10242 ,  H05K2201/10992 ,  H05K2203/048 ,  H05K3/4015 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/12361

摘要： Positive mechanical alignment is provided between substrates using micro-bump contacts by forming "detented" conductive bump contacts on one substrate having a concave end which receive and align the generally convex contour of bump contacts on the other substrate. Various configurations of concavities and convexities are described. Flux may be disposed in the concave end of the detented bump contact to promote formation of joints between the concave and convex bump contacts. Both bump contacts may be formed of reflowable material, such as solder, or one or the other of the contacts may be formed of a non-reflowable material which may also function as a standoff between the two substrates. Each substrate is provided with a plurality of bump contacts, and one substrate may be provided with a combination of convex and concave bump contacts corresponding to concave and convex bump contacts on the other substrate. The inventive technique is useful for joining die-to-die, die-to-substrate, or package-to-substrate.

摘要翻译： 通过在具有凹端的一个基板上形成“定位”的导电凸块触点，在衬底之间提供正的机械对准，使用微凸块触点，该凹入端接收并对准另一个基板上的凸块触点的大致凸形轮廓。 描述各种凹凸的构造。 通量可以设置在止动凸起接触的凹入端中，以促进凹凸凸点触点之间的接合部的形成。 两个凸起触点可以由可回流材料（例如焊料）形成，或者一个或另一个触点可以由也可用作两个基板之间的间隙的不可回流材料形成。 每个基板设置有多个凸块触点，并且一个基板可以设置有与另一个基板上的凹凸凸点接触对应的凸凸触点的组合。 本发明的技术可用于连接管芯到管芯，管芯到衬底或封装到衬底。

公开(公告)号：US5453583A

公开(公告)日：1995-09-26

申请号：US58117

申请日：1993-05-05

申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

IPC分类号： H01L23/485 ,  H05K1/00

CPC分类号： H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351

摘要： A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads. Other aspects involve disposing the bond pads into an elongated pattern to minimize thermal displacement primarily in one direction, and orienting a lead frame or the like to accommodate any thermal migration of the bond pads in a controlled direction.

摘要翻译： 减小半导体器件组件中的接合焊盘上的热诱导机械应力的技术是通过将接合焊盘分组成内部区域（通常远离外围部分）相对较小（与模具的总面积相比）的子区域 ）的死亡。 通过保持接合焊盘布局小（紧密组合，或沿着单个行或轴定向），接合焊盘之间的差异热诱导位移被最小化，或者被控制在一个维度上。 此外，接合焊盘可以设置在靠近管芯的热膨胀（中心）的中心附近的小区域中，或靠近发热电路元件，以最小化单个接合焊盘与质心或电路元件的绝对热位移。 可以使用重叠的子区域图案，并且分组的接合焊盘可以与传统的芯片周边定位的焊盘结合使用（包括重叠）。 其他方面涉及将接合焊盘设置成细长图案以最小化主要在一个方向上的热位移，并且定向引线框架等以适应接合焊盘在受控方向上的任何热迁移。