公开(公告)号：US4912340A

公开(公告)日：1990-03-27

申请号：US260942

申请日：1988-10-21

申请人： Philip S. Wilcox ,  Stephen K. Sunter ,  Nayan Mehta

发明人： Philip S. Wilcox ,  Stephen K. Sunter ,  Nayan Mehta

IPC分类号： H03K5/151

CPC分类号： H03K5/1515

摘要： In order to provide for clocking master/slave flip-flops in complex circuits by means of non-overlapping two-phase clocks, a clock generator for providing two clocks signals for use with two-phase flip-flops, comprises a settable latch and a gating device. The settable latch has a data input connected to a reference source, a set input connected to receive one of the two clock signals and a clock input connected to receive the other of the two clock signals. The gating device has one input connected to receive such one of the two clock signals and a second input connected to the output of the settable latch. The output of the gating device, which corresponds to the other of the two clock signals, is connected to the clock input of the settable latch, the arrangement being such that when the settable latch has been set by a transition of the one clock signal resetting of the settable latch is enabled by the other clock signal. A digital circuit, for example an integrated circuit, may have a number of latches, each comprising, for example the first stage of a master/slave flip-flop, and such a clock generator for operating them. Preferably the latches are arranged in groups, conveniently as a macro sub-block, with a clock generator for operating each group. Preferably the settable latch is similar in construction to the latches being controlled.

摘要翻译： 为了通过非重叠的两相时钟在复杂电路中提供时钟主/从触发器，用于提供与两相触发器一起使用的两个时钟信号的时钟发生器包括可设置的锁存器和 门控装置 可设置的锁存器具有连接到参考源的数据输入端，被连接以接收两个时钟信号之一的设定输入和连接以接收两个时钟信号中的另一个的时钟输入。 选通装置具有连接的一个输入端以接收两个时钟信号中的一个，以及连接到可设置的锁存器的输出的第二输入。 对应于两个时钟信号中的另一个的选通装置的输出连接到可设置的锁存器的时钟输入，该布置使得当可设置的锁存器已经通过一个时钟信号复位的转变而被设置 的可设置锁存器由另一个时钟信号使能。 数字电路，例如集成电路，可以具有多个锁存器，每个锁存器包括例如主/从触发器的第一级，以及用于操作它们的时钟发生器。 优选地，锁存器被方便地布置成宏子块，具有用于操作每个组的时钟发生器。 优选地，可设置的闩锁在结构上与被控制的闩锁相似。