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48 条记录 (耗时 0.043 秒)

    FM signal oscillator circuit and modulation level control method
    21.
    发明授权
    FM signal oscillator circuit and modulation level control method 失效

    公开(公告)号：US06545557B2

    公开(公告)日：2003-04-08

    申请号：US09880918

    申请日：2001-06-15

    申请人： Minoru Nagata

    发明人： Minoru Nagata

    IPC分类号： H03C302

    CPC分类号： H03C3/04 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1293

    摘要： An FM signal oscillator circuit includes a resonator having a graded- or abrupt-junction variable capacitance diode that is producible through standard IC manufacturing processes but causes an inconstant modulation level. The FM signal oscillator circuit, therefore, is provided with a function of maintaining a constant modulation level irrespective of oscillation frequencies. Namely, to maintain a constant modulation level without regard to oscillation frequencies that change depending on a control voltage applied to the variable capacitance diode, the FM signal oscillator circuit employs a variable gain amplifier whose gain changes in response to the control voltage. The variable gain amplifier amplifies a modulating signal, and the amplified modulating signal is superimposed onto the control voltage. The superimposed signal is applied to the variable capacitance diode, and a driver of the FM signal oscillator circuit provides an FM signal whose modulation level is constant irrespective of the control voltage that may vary. With this configuration, the FM signal oscillator circuit is producible as an integrated circuit through standard IC manufacturing processes at low cost.

    Radio paging system with voice transfer function and radio pager
    23.
    发明授权
    Radio paging system with voice transfer function and radio pager 失效
    具有语音传输功能的无线寻呼系统和无线寻呼机

    公开(公告)号：US5412719A

    公开(公告)日：1995-05-02

    申请号：US5315

    申请日：1993-01-15

    申请人： Nobuo Hamamoto ,  Tadashi Onishi ,  Tatsundo Suzuki ,  Minoru Nagata ,  Kenichi Mizuishi ,  Yosuke Tyojamori

    发明人： Nobuo Hamamoto ,  Tadashi Onishi ,  Tatsundo Suzuki ,  Minoru Nagata ,  Kenichi Mizuishi ,  Yosuke Tyojamori

    IPC分类号： G08B3/10 ,  G08B5/22 ,  H04M3/533 ,  H04M11/02 ,  H04W88/18 ,  H04K1/00

    CPC分类号： H04W88/187 ,  G08B3/1025 ,  G08B5/229 ,  H04M11/022 ,  H04M3/533 ,  H04M2203/609

    摘要： A radio paging system with voice transfer function for transmitting a voice message input from an ordinary push-button telephone set to a small-sized receive-only unsophisticated radio pager. A paging station is provided to transmit by radio the message from a telephone network to the radio pager as follows: voice information constituting the message is first converted from analog to digital format, compressed, stored in memory, and scrambled by a privacy function part for transmission. The radio pager in turn demodulates the received information, stores it in memory, retrieves a necessary message therefrom as designated, descrambles the designated message from scrambled state, expands the message from compressed state, and outputs the message as an audible output. In this manner, the user carrying the radio pager is able to get the message from the caller without the risk of being tapped by a third party.

    摘要翻译： 一种具有语音传输功能的无线寻呼系统，用于将从普通按钮式电话机输入的语音消息发送到小型仅接收非专用无线寻呼机。 提供寻呼站，通过无线电将消息从电话网络传送到无线寻呼机，如下：构成消息的语音信息首先从模拟数字格式转换，压缩，存储在存储器中，并由隐私功能部分加扰 传输。 无线寻呼机依次对接收到的信息进行解调，将其存储在存储器中，按指定的方式从中取出必要的消息，从指定的消息中解扰，从扩展状态扩展消息，并将消息作为声音输出输出。 以这种方式，携带无线寻呼机的用户能够从呼叫者获得消息，而不会被第三方窃听。

    IIL semiconductor memory including arrangement for preventing information loss during read-out
    24.
    发明授权
    IIL semiconductor memory including arrangement for preventing information loss during read-out 失效
    IIL半导体存储器包括用于在读出期间防止信息丢失的装置

    公开(公告)号：US4589096A

    公开(公告)日：1986-05-13

    申请号：US476269

    申请日：1983-03-17

    申请人： Kenji Kaneko ,  Takahiro Okabe ,  Minoru Nagata

    发明人： Kenji Kaneko ,  Takahiro Okabe ,  Minoru Nagata

    IPC分类号： G11C11/411 ,  G11C11/416 ,  H01L21/8229 ,  H01L27/102 ,  G11C11/00

    CPC分类号： G11C11/416 ,  G11C11/4113 ,  H01L27/1025

    摘要： A semiconductor memory having memory cells in each of which emitter terminals and first collector terminals of two IIL unit circuits are cross-connected to each other, injector regions and a common emitter region of the two IIL unit circuits are respectively connected to upper and lower word lines, and second collectors of the IIL unit circuits are respectively connected to a pair of bit lines that are respectively connected through load elements to a power source higher in voltage than the lower word line. This serves to hold the bit line potential higher than the lower word line potential to ensure that transistors formed by the second collectors, the emitters and the bases are inversely operated to prevent information loss during a read operation.

    摘要翻译： 具有存储单元的半导体存储器，其中两个IIL单元电路的发射极端子和第一集电极端子彼此交叉连接，两个IIL单元电路的喷射器区域和公共发射极区域分别连接到上部和下部单元 线路和IIL单元电路的第二集电极分别连接到分别通过负载元件连接到电压高于下字线的电源的一对位线。 这用于将位线电位保持为高于低字线电位，以确保由第二集电极，发射极和基极形成的晶体管反向操作，以防止读操作期间的信息丢失。

    Complementary Schottky transistor logic circuit
    25.
    发明授权
    Complementary Schottky transistor logic circuit 失效
    互补肖特基晶体管逻辑电路

    公开(公告)号：US4433258A

    公开(公告)日：1984-02-21

    申请号：US245163

    申请日：1981-03-18

    申请人： Kenji Kaneko ,  Takahiro Okabe ,  Minoru Nagata ,  Yutaka Okada

    发明人： Kenji Kaneko ,  Takahiro Okabe ,  Minoru Nagata ,  Yutaka Okada

    IPC分类号： H03K19/082 ,  H03K19/091 ,  H03K19/092 ,  H03K19/088

    CPC分类号： H03K19/0915 ,  H03K19/082

    摘要： A logic circuit is provided which includes a plurality of basic circuits each of which has a pnp (or npn) transistor as a constant current load and at least one npn (or pnp) transistor each as a driver with a clamping Schottky diode. The base of the driver transistor is used as an input terminal and the collector thereof is used as an output terminal, for each basic circuit and the output terminal of the preceding stage basic circuit is coupled directly to the input terminal of the subsequent stage basic circuit. In order to prevent current hogging the load current supplied from the preceding stage constant current load transistor is set to operate the subsequent stage driver transistor in a saturation made when the subsequent stage driver transistor is in the ON state.

    摘要翻译： 提供了一种逻辑电路，其包括多个基本电路，每个基本电路具有作为恒定电流负载的pnp（或npn）晶体管和每个具有钳位肖特基二极管的驱动器的至少一个npn（或pnp）晶体管）。 驱动晶体管的基极用作输入端子，其集电极用作输出端子，对于每个基本电路，前级基本电路的输出端子直接耦合到后级基本电路的输入端子 。 为了防止电流偏移，设定从前一级恒流负载晶体管提供的负载电流，以使后级级驱动晶体管处于导通状态时产生的饱和度使后级级驱动晶体管工作。

    Large scale integrated circuit array of unit cells and method of manufacturing same
    26.
    发明授权
    Large scale integrated circuit array of unit cells and method of manufacturing same 失效
    单位电池的大规模集成电路阵列及其制造方法

    公开(公告)号：US3983619A

    公开(公告)日：1976-10-05

    申请号：US394631

    申请日：1973-09-06

    申请人： Masaharu Kubo ,  Minoru Nagata ,  Keikichi Moriwaki

    发明人： Masaharu Kubo ,  Minoru Nagata ,  Keikichi Moriwaki

    IPC分类号： H01L27/118 ,  B01J17/00

    CPC分类号： H01L27/11803 ,  Y10S257/909

    摘要： A semiconductor LSI array comprising a plurality of unit cells arranged in rows, each of which cells has operation terminals, input terminals and output terminals positioned in a standardized relation. A set of runways are provided on the unit cells for each row so that the runways may be connected to corresponding operation terminals and that input terminals may be opposed to output terminals with respect to the runways.

    摘要翻译： 一种半导体LSI阵列，包括排列成行的多个单位单元，每个单元具有操作终端，输入端子和以标准化关系定位的输出端子。 在每一行的单位单元上提供一组跑道，使得跑道可以连接到相应的操作终端，并且输入终端可以相对于跑道相对于输出终端。

    Temperature compensation circuit
    27.
    发明授权
    Temperature compensation circuit 失效
    温度补偿电路

    公开(公告)号：US08427227B2

    公开(公告)日：2013-04-23

    申请号：US13403121

    申请日：2012-02-23

    申请人： Koji Horie ,  Minoru Nagata

    发明人： Koji Horie ,  Minoru Nagata

    IPC分类号： G05F3/02 ,  H03K17/14

    CPC分类号： H03F1/302 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/447 ,  H03F2200/451

    摘要： In one embodiment, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region, and a transistor which is supplied with the bias current. The bias circuit includes first to third transistors, a fourth transistor through which a first current flows, a fifth transistor, a sixth transistor through which a second current flows, and a control circuit having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current. The bias circuit generates a third current by adding the first current to the second current, and outputs the bias current that is the third current or a fourth current depending on the third current.

    摘要翻译： 在一个实施例中，温度补偿电路包括偏置电路，该偏置电路被配置为输出具有与低温区域中的绝对温度成比例增加的电流值的偏置电流，并且具有比与绝对值成比例的电流值更大的电流值 高温区域的温度，以及被提供偏置电流的晶体管。 偏置电路包括第一至第三晶体管，第一电流流经的第四晶体管，第五晶体管，第二电流流经的第六晶体管，以及具有能够与外部电阻器连接的连接端子的控制电路， 调整第二电流的大小。 偏置电路通过将第一电流加到第二电流来产生第三电流，并根据第三电流输出作为第三电流或第四电流的偏置电流。

    CURRENT MIRROR CIRCUIT
    28.
    发明申请
    CURRENT MIRROR CIRCUIT 失效
    当前镜像电路

    公开(公告)号：US20110304387A1

    公开(公告)日：2011-12-15

    申请号：US13046953

    申请日：2011-03-14

    申请人： Kenichi Hirashiki ,  Norio Hagiwara ,  Tsutomu Nakashima ,  Minoru Nagata

    发明人： Kenichi Hirashiki ,  Norio Hagiwara ,  Tsutomu Nakashima ,  Minoru Nagata

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262

    摘要： In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.

    摘要翻译： 在一个实施例中，电流镜电路包括第一至第四绝缘栅场效应晶体管（FET）和偏置电路。 第一和第二FET的栅电极彼此连接。 第三FET的源电极连接到第一FET的漏电极，第三FET的漏电极连接到第一和第二FET的栅电极以及电流输入端。 第四FET的栅电极与第三FET的栅电极连接，第四FET的源电极与第二FET的漏极连接，第四FET的漏极成为电流输出端。 偏置电路被配置为向第三和第四FET的栅电极提供偏置电压。