公开(公告)号：US20150039940A1

公开(公告)日：2015-02-05

申请号：US13956171

申请日：2013-07-31

Applicant: Oracle International Corporation

Inventor： Paul N. Loewenstein ,  Basant Vinaik

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/0721 ,  G06F11/26 ,  G06F12/00

Abstract: A system and method for verifying that a processor design having caches conforms to a specific memory model. The caches might not be maintained coherent in real time. Specifically, the system and method make use of a checker that conforms to the memory model, a time-stamping scheme, and a store buffering scheme to identify a bug(s) in the processor design that violates the memory model and/or loads an incorrect value in response to a load instruction.

Abstract translation: 一种用于验证具有高速缓存的处理器设计符合特定存储器模型的系统和方法。 缓存可能不会保持实时一致。 具体地说，系统和方法利用符合存储器模型的检验器，时间戳方案和存储缓冲方案来识别违反存储器模型的处理器设计中的错误和/或加载 响应于加载指令的值不正确。