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    Frequency calibration loop circuit
    21.
    发明授权
    Frequency calibration loop circuit 失效
    频率校准回路电路

    公开(公告)号：US08031009B2

    公开(公告)日：2011-10-04

    申请号：US12581105

    申请日：2009-10-16

    申请人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/085 ,  H03L7/095 ,  H03L7/18 ,  H03L7/081

    CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

    摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

    摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

    Digital lock detector and frequency synthesizer using the same
    22.
    发明授权
    Digital lock detector and frequency synthesizer using the same 有权
    数字锁定检测器和频率合成器使用相同

    公开(公告)号：US07956658B2

    公开(公告)日：2011-06-07

    申请号：US12607395

    申请日：2009-10-28

    申请人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

    摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

    摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

    DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME
    23.
    发明申请
    DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME 有权
    使用数字锁定检测器和频率合成器

    公开(公告)号：US20100271072A1

    公开(公告)日：2010-10-28

    申请号：US12607395

    申请日：2009-10-28

    申请人： Ja Yol LEE ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Ja Yol LEE ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03K5/22 ,  H03B21/00

    CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

    摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

    摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

    CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME
    24.
    发明申请
    CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME 审中-公开
    具有可变电容的电容器和包括其的数字控制振荡器

    公开(公告)号：US20100134195A1

    公开(公告)日：2010-06-03

    申请号：US12629742

    申请日：2009-12-02

    申请人： Ja Yol LEE ,  Byung Hun Min ,  Seong Do Kim ,  Hyun Kyu Yu

    发明人： Ja Yol LEE ,  Byung Hun Min ,  Seong Do Kim ,  Hyun Kyu Yu

    IPC分类号： H03B5/12 ,  H01L27/06

    CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1265

    摘要： There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.

    摘要翻译： 提供具有可变电容的电容器，其通过使用CMOS工艺将开关施加到金属氧化物金属（MOM）结构板电容器上，根据控制信号形成不同的电容。 电容器包括堆叠结构，其包括多个金属层，包括第一金属层和分别介于多个金属层之间的多个电介质层，以及开关部分，其包括至少一个开关，该开关的一侧连接至至少一个 除了第一金属层之外的多个金属层中的金属层。 开关的第一金属层和另一侧用作电容器的两端，并且在控制开关的短路/断开时，至少两个电容设置在电容器的两个端子之间。

    Automatically gain controllable linear differential amplifier using variable degeneration resistor
    25.
    发明授权
    Automatically gain controllable linear differential amplifier using variable degeneration resistor 有权
    使用可变退化电阻自动增益可控线性差分放大器

    公开(公告)号：US06605996B2

    公开(公告)日：2003-08-12

    申请号：US10039542

    申请日：2001-12-31

    申请人： Hyun Kyu Yu ,  Sang-Gug Lee ,  Mun Yang Park ,  Seong-Do Kim ,  Yong-Sik Youn ,  Seon-Ho Han ,  Nam-Soo Kim

    发明人： Hyun Kyu Yu ,  Sang-Gug Lee ,  Mun Yang Park ,  Seong-Do Kim ,  Yong-Sik Youn ,  Seon-Ho Han ,  Nam-Soo Kim

    IPC分类号： H03F345

    CPC分类号： H03G1/007 ,  H03F3/45179 ,  H03F2203/45492 ,  H03G1/0023

    摘要： An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity. The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.

    摘要翻译： 公开了一种使用可变退化电阻的自动增益可控线性差分放大器。 线性差分放大器包括输入端，偏置电流源，负载单元，第一MOS晶体管和第二MOS晶体管。 本发明的线性差分放大器可以根据输入信号控制放大增益，并提高线性度IIP3，而不需要通过提高线性度而引起的附加功耗。 自动增益可控线性差分放大器使用NMOS / PMOS晶体管，因此可以更方便，高效地实现放大器的集成过程。

    TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME
    27.
    发明申请
    TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME 有权
    时数转换器和所有数字相位锁定环路

    公开(公告)号：US20110148490A1

    公开(公告)日：2011-06-23

    申请号：US12956498

    申请日：2010-11-30

    申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/08 ,  H03M1/50

    CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

    摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

    摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

    FREQUENCY CALIBRATION LOOP CIRCUIT
    28.
    发明申请
    FREQUENCY CALIBRATION LOOP CIRCUIT 失效
    频率校准环路

    公开(公告)号：US20100134192A1

    公开(公告)日：2010-06-03

    申请号：US12581105

    申请日：2009-10-16

    申请人： Byung Hun MIN ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Byung Hun MIN ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/00

    CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

    摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.

    摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器根据控制值调节振荡频率; 一个可编程除法器根据分频比划分振荡频率; 通过使用参考频率对分频频率的时钟数进行计数的计数器; 输出通过从参考比较值中减去计数时钟数而得到的值的频率检测器，通过将频率通道字（FCW）指令值除以可编程分压器的最小分频比而获得的值作为控制值 的振荡器。

    Digital receiver
    29.
    发明授权
    Digital receiver 有权
    数字接收机

    公开(公告)号：US08509353B2

    公开(公告)日：2013-08-13

    申请号：US12818510

    申请日：2010-06-18

    申请人： Seon-Ho Han ,  Hyun Kyu Yu

    发明人： Seon-Ho Han ,  Hyun Kyu Yu

    IPC分类号： H03K9/00

    CPC分类号： H04B1/0025 ,  H04B1/001

    摘要： In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs subsampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain.

    摘要翻译： 在数字接收机中，噪声衰减和信号幅度映射可变放大单元包括滤波器和放大器，对模拟信号进行放大和频带滤波，并衰减白噪声和除频带信号之外的干扰信号。 ADC在期望信号的载波频率上执行子采样，并通过使用采样频率对已经通过噪声衰减和信号幅度映射可变放大单元的模拟信号进行数字信号的期望信号的频带上的过采样， 的直接转换频带或中频带。 ADC具有用于处理期望信号和与期望信号相邻的不期望信号的动态范围。 数字信号处理单元转换数字信号的信号频率或数字滤波数字信号内的不需要的信号，并通过数字调节增益来处理数字信号。