公开(公告)号：US10651268B2

公开(公告)日：2020-05-12

申请号：US16009976

申请日：2018-06-15

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Ye Lu ,  Chao Song

IPC: H01L29/00 ,  H01L49/02

Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

公开(公告)号：US10553531B2

公开(公告)日：2020-02-04

申请号：US15710737

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Chao Song ,  Xuhao Huang ,  Marzio Pedrali-Noy

IPC: H01L23/522 ,  H01P1/203 ,  H05K3/30 ,  H01L21/74 ,  H01L21/82 ,  H01L27/01 ,  H01L49/02

Abstract: A process-invariant RC circuit is formed by patterning a metal layer using the same mask pattern to form a metal layer resistor and a metal layer capacitor. The same mask pattern results in the metal layer resistor and the metal layer capacitor each having a plurality of longitudinally-extending fingers having the same width and separation.

公开(公告)号：US10269490B2

公开(公告)日：2019-04-23

申请号：US15687234

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Kevin Jia-Nong Wang ,  Chao Song

IPC: H01G4/012 ,  H01G4/248

Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.