Decoding side intra-prediction derivation for video coding
    21.
    发明申请
    Decoding side intra-prediction derivation for video coding 审中-公开
    用于视频编码的解码侧帧内预测推导

    公开(公告)号:US20120106640A1

    公开(公告)日:2012-05-03

    申请号:US12945949

    申请日:2010-11-15

    IPC分类号: H04N7/12

    摘要: Decoding side intra-prediction derivation for video coding. Just decoded pixels within a given picture (image) (e.g., such as a given picture (image) within video data) are employed for decoding other pixels within that very same picture (image) using prediction vectors extending from the just decoded pixels to the pixels currently being decoded. In one instance, this intra-prediction operation in accordance with video or image processing can also operate using relatively limited information provided from the device that provides or transmits the video data to the device in which it undergoes processing. Coarse and/or refined direction information corresponding to these prediction vectors may be provided from the device that provides or transmits the video data to the device in which it undergoes processing.

    摘要翻译: 用于视频编码的解码侧帧内预测推导。 使用给定图像(图像)内的解码像素(例如,视频数据中的给定图像(图像))来解码使用从刚刚解码的像素延伸到相同图像的图像(图像)内的其他像素 当前正在解码的像素。 在一种情况下,根据视频或图像处理的该帧内预测操作也可以使用从提供或发送视频数据到其进行处理的设备的设备提供的相对有限的信息来进行操作。 可以从提供或发送视频数据到其进行处理的设备的设备提供对应于这些预测向量的粗略和/或精细方向信息。

    Turbo coding having combined turbo de-padding and rate matching de-padding
    22.
    发明申请
    Turbo coding having combined turbo de-padding and rate matching de-padding 失效
    Turbo编码具有组合的turbo去填充和速率匹配去填充

    公开(公告)号:US20120063537A1

    公开(公告)日:2012-03-15

    申请号:US13296348

    申请日:2011-11-15

    IPC分类号: H04L27/00

    摘要: Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving.

    摘要翻译: Turbo编码具有组合的turbo去填充和速率匹配去填充。 提出了一种方法,通过该方法,单个模块可操作以根据turbo编码执行零比特解除填充和伪比特解除填充。 在进行turbo编码之前,可以对输入信息流执行零填充。 来自turbo编码模块的3个输出中的一个或多个(例如,系统比特,奇偶校验1比特和奇偶校验2比特)然后也可以经历伪比特填充。 此后,这3个流(其中一些或全部可能经历了伪位填充)经历子块交织。 在所有这些操作已经发生之后,可以采用单一组合的去填充模块来执行从填充子块交错的三个流中的每一个中去除任何零填充位和任何虚拟填充位。

    Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size
    23.
    发明授权
    Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size 失效
    降低复杂度ARP(几乎规则排列)交错,提供适应任何可能的turbo码块大小的灵活的粒度和并行性

    公开(公告)号:US08065587B2

    公开(公告)日:2011-11-22

    申请号:US11811013

    申请日:2007-06-07

    IPC分类号: H03M13/00

    摘要: Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

    摘要翻译: 降低复杂度ARP(几乎规则排列)交错,提供适应任何可能的turbo码块大小的灵活的粒度和并行性。 提出了一种新颖的方法,当仅需要非常少量的虚拟位时,可以采用任何期望的turbo码块大小。 这种方法也可直接适用于平行turbo解码,其中可以采用任何期望的并行度。 或者,也可以在完全非并行实现中使用少至一个turbo解码器。 此外,该方法允许存储少量参数以适应各种各样的交错。

    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
    26.
    发明授权
    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices 失效
    具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码

    公开(公告)号:US07900127B2

    公开(公告)日:2011-03-01

    申请号:US12533306

    申请日:2009-07-31

    IPC分类号: G06F11/00

    摘要: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译: 具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成,并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI(循环移位身份)子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上,另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵(即,其中的所有元素为零“0”)。

    Parallel concatenated code with soft-in soft-out interactive turbo decoder
    27.
    发明授权
    Parallel concatenated code with soft-in soft-out interactive turbo decoder 有权
    并行级联代码与软入软交互式turbo解码器

    公开(公告)号:US07715503B2

    公开(公告)日:2010-05-11

    申请号:US12534604

    申请日:2009-08-03

    IPC分类号: H04L5/12 H04L23/02

    摘要: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

    摘要翻译: 一种并行级联(Turbo)编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列,或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法(例如块或随机交织)的加法规则进行交织,其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数),因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的,那么输出元组可以从编码器顺序选择,也不会丢失元组。 如果输入元组包含多个比特,那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器,或者所有编码器可以具有交织器,无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

    Header encoding for single carrier (SC) and/or orthogonal frequency division multiplexing (OFDM) using shortening, puncturing, and/or repetition
    28.
    发明申请
    Header encoding for single carrier (SC) and/or orthogonal frequency division multiplexing (OFDM) using shortening, puncturing, and/or repetition 有权
    使用缩短,穿孔和/或重复的单载波(SC)和/或正交频分复用(OFDM)的报头编码

    公开(公告)号:US20100115372A1

    公开(公告)日:2010-05-06

    申请号:US12612648

    申请日:2009-11-04

    IPC分类号: H03M13/05 G06F11/10

    摘要: Header encoding for SC and/or OFDM signaling using shortening, puncturing, and/or repetition in accordance with encoding header information within a frame to be transmitted via a communication channel employs different respective puncturing patterns as applied to different portions thereof. For example, a first puncturing pattern is applied to a first portion of the frame, and a second puncturing pattern is applied to a second portion of the frame (the second portion may be a repeated version of the first portion). Shortening (e.g., by padding 0-valued bits thereto) may be made to header information bits before they undergo encoding (e.g., in an LDPC encoder). One or both of the information bits and parity/redundancy bits output from the encoder undergo selective puncturing. Moreover, one or both of the information bits and parity/redundancy bits output from the encoder may be repeated/spread before undergoing selective puncturing to generate a header.

    摘要翻译: 根据要通过通信信道发送的帧内的编码头信息,使用缩短,删截和/或重复的SC和/或OFDM信令的报头编码,采用不同的相应的打孔图案,应用于其不同部分。 例如,将第一穿孔图案应用于框架的第一部分,并且将第二穿孔图案应用于框架的第二部分(第二部分可以是第一部分的重复版本)。 在进行编码之前(例如,在LDPC编码器中),可以缩短(例如,通过填充0值比特)到头信息比特。 从编码器输出的信息位和奇偶校验/冗余位中的一个或两个进行选择性穿孔。 此外,可以在进行选择性穿孔之前重复/扩展从编码器输出的信息比特和奇偶校验/冗余比特中的一个或两个以产生报头。

    Short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications
    30.
    发明授权
    Short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications 失效
    适用于高速以太网应用的短长度LDPC(低密度奇偶校验)码和调制

    公开(公告)号:US07559010B2

    公开(公告)日:2009-07-07

    申请号:US11190657

    申请日:2005-07-27

    IPC分类号: H03M13/00

    摘要: A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.

    摘要翻译: 适用于高速以太网应用的短长度LDPC(低密度奇偶校验)码和调制。 在一些情况下,可以在IEEE 802.3an(10GBASE-T)任务组正在开发的推荐实践中采用短长度LDPC码和调制。 IEEE 802.3an(10GBASE-T)工作组已委托开发和标准化通信协议,特别适用于通过4线双绞线电缆进行以太网操作。 本文中呈现了新的LDPC码,星座的一些可能的实施例和对应的映射以及LDPC码的各种奇偶校验矩阵H的可能实施例,以提供比本领域中存在的其它提出的LDPC码更好的总体性能 的高速以太网应用。 此外,该提出的LDPC码可以使用比在该技术空间中存在的其它提出的LDPC码要求更低的复杂度的通信设备进行解码。