Abstract:
A thin film transistor array panel includes a first insulation substrate, a gate line and a data line which are positioned on the first insulation substrate, are insulated from each other, and cross each other, a thin film transistor connected to the gate line and the data line, an organic film positioned on the thin film transistor, a second passivation layer which is positioned on the organic film and defines a plurality of second openings therein, a common electrode positioned on the second passivation layer, and a pixel electrode positioned in the plurality of second openings, where a thickness of the common electrode is larger than a thickness of the pixel electrode.